RISC-V: Emulation and Rich, Non-Intrusive Analytics Address - - PowerPoint PPT Presentation

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RISC-V: Emulation and Rich, Non-Intrusive Analytics Address - - PowerPoint PPT Presentation

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RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity Embedded World | 27 Feb 2018 UltraSoC: Corporate Overview Tier-1 VC-funded start-up Automotive Recently completed round D ($6M) ARMv8 Founded 2009

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SLIDE 1

RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity

Embedded World | 27 Feb 2018

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SLIDE 2
  • VC-funded start-up
  • Recently completed round D ($6M)
  • Founded 2009
  • Headquarters in Cambridge UK
  • 44 patents
  • New Chairman October 2017
  • Alberto Sangiovanni-Vincentelli
  • Industry leaders adopting UltraSoC
  • Silicon-proven with multiple customers

UltraSoC: Corporate Overview

Embedded World 2018 2 Commercial in Confidence

Tier-1 Automotive ARMv8 Server

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SLIDE 3
  • Founded in 1982 to deliver electronic design automation solutions
  • Acquired by Siemens in March 2017
  • Mentor has the broadest industry portfolio of best-in-class products
  • For IC, FPGA, boards, wire harness, and systems
  • The only EDA company with embedded software products
  • Helps engineers conquer design challenges in the increasingly complex worlds of

board and chip design

Mentor Graphics: Corporate Overview

3 Embedded World 2018 Commercial in Confidence

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SLIDE 4
  • SoC with multi-processors, video and graphic IP
  • Heterogeneous multi-core; HW+SW co-integration
  • Simulation tools struggle with capacity and debug
  • Some problems only seen in real silicon
  • Post-silicon: difficult to monitor large SoCs
  • Design cost increasing at +43.7% CAGR
  • IP integration cost increasing +77.2% CAGR
  • UltraSoC gives insight to fix these issues

The SoC productivity gap

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Systemic Complexity & Increasing Cost 1

Methodology Number of transistors in CPU Start of Moore’s Law

Development Methodology Evolution

Smartphone (courtesy VIA, Inc.)

Embedded World 2018 Commercial in Confidence

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SLIDE 5
  • SoC design cycles lengthening and costs growing
  • Debugging problematic silicon is expensive
  • Optimization is hard (especially HW+SW)
  • Lost Product Sales from late Time-In-Market
  • Lost Product Sales due to Reduced Time-In-Market
  • ”First to market makes 3x lifetime profit” – PRTM
  • Spend a few thousand gates to save months in TTM

and $M in development

The SoC productivity gap

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Cost of failure is higher than ever 2

4 12 26 42 61 91 129 173 227 329

1 8 n m 1 3 n m 9 n m 6 5 n m 4 5 / 4 n m 3 2 / 2 8 n m 2 2 / 2 n m 1 6 / 1 4 n m 1 n m 7 n m SoC Design Cost ($m)

Costs are growing rapidly

Producing a complex SoC typically costs $170m+…. ….or $12m per month, time is valuable!

Embedded World 2018 Commercial in Confidence

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SLIDE 6

Classical “Processor Centric” View

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System Requirements

Sub-System Design HW/SW Block Design HW/SW Implementation Module Integration Sub-System Integration System Acceptance

Validation

Validation

Validation

T e s t i n g D e v e l

  • p

m e n t

Simulation/Prototyping/ Emulation based debug

Embedded World 2018 Commercial in Confidence

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SLIDE 7

Pre-silicon today (1)

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Tools exist for debugging & analysis in virtual world BUT

  • Many cannot support HW+SW
  • Simulation cannot detect subtle,

system-wide bugs

  • Emulation powerful & far faster

Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Embedded World 2018 Commercial in Confidence

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SLIDE 8

Pre-silicon with Mentor Graphics

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Embedded World 2018 Commercial in Confidence

Expands & completes pre-silicon with very powerful tools that understand HW + SW

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SLIDE 9

Digital Circuit Verification / Validation Challenge

  • A large digital integrated circuit can contain 1 billion gates or more
  • A task like booting the Android OS takes billions of cycles
  • Modeling large integrated circuits for the workloads required for verification takes more

computing than can be accomplished on CPU farms with 1000s of CPUs for many years

  • Emulation is a key technology to address this challenge

9 Embedded World 2018 Commercial in Confidence

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SLIDE 10

What is an Emulator?

§ An emulator is special purpose hardware for modeling digital integrated circuits § Emulators typically run 1,000 to 10,000 times faster than a SW simulator § It contains programmable logic elements and programmable interconnects used to implement the circuit being verified § It has trace logic that can record the state of the entire circuit for later analysis § The state of the circuit being verified can be saved and restored § Veloce Strato supports designs up to 15 billion gates and up to 64 concurrent users

10 Embedded World 2018 Commercial in Confidence

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SLIDE 11

Power Analysis on Veloce

Veloce Activity Plot Signoff Power Plot

ON ON ON OFF OFF

Identification of Power peaks

Large peaks (~1us) -> e.g. Supply integrity Narrow peaks (~1ns) -> e.g. IR-Drop

OFF

Verification of Power Domains Usage via UPF Hot Spots Identification Optimization targets, Local IR-Drop,…

Should be OFF

Close Correlation Power Surges Identification dI/dt voltage drop Electro-migration High power on very long periods Power Trends Compare activity plots across RTL drops

11 Embedded World 2018 Commercial in Confidence

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SLIDE 12

Veloce Deterministic ICE App

  • Emulator is connected to external devices
  • Must interact with real devices in real-time
  • Cannot be slowed or stopped to perform, tracing

debug or analysis

  • Input (stimulus) from real devices are recorded
  • After run is complete, design is “replayed”

with recorded stimulus

  • During this run, tracing, debug, and analysis can be

performed

  • Design can be saved and restored
  • Allows deep analysis of designs with “hardware in the

loop” including power analysis and full waveform views

D i s k R e a d

SoC Design

Network Input

CPU Timer Events I/O Devices K e y b

  • a

r d & M

  • u

s e I n p u t

SoC Design

12 Embedded World 2018 Commercial in Confidence

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SLIDE 13

Visualizer Debug Environment

  • Common waveform and analysis platform for all

Mentor’s design tools

  • Enables data collected from logic simulation, emulation, FPGA

prototyping, and virtual prototyping to be combined and correlated

  • Easy to use
  • Powerful analysis capabilities
  • High capacity
  • Handles full design traces of billion gate designs over millions
  • f clock cycles

13 Embedded World 2018 Commercial in Confidence

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SLIDE 14

Marching Waveforms

  • Marching waveforms allow users to view

design traces as they are collected on the emulator

  • Waveforms are uploaded periodically
  • Every second or 1 million clocks,

which ever occurs first\

  • Enables interactive debug of designs on

Veloce

14 Embedded World 2018 Commercial in Confidence

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SLIDE 15

Powerful, Easy Searching and Filtering

  • Search and Filter in any window to find objects
  • Advanced search adds color tags to a search

highlighting key traces

15 Embedded World 2018 Commercial in Confidence

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SLIDE 16

TimeCone - Find Root Cause of an Event or X

Trace values back in time through combinational AND sequential elements to find root cause

16 Embedded World 2018 Commercial in Confidence

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SLIDE 17

FSM Debug

  • View complete FSM state transitions diagram and table

Previous State Active State Inactive State

17 Embedded World 2018 Commercial in Confidence

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SLIDE 18

Post-silicon today

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Post-silicon tools do exist BUT:

  • Are inconsistent
  • Operate in silos; usually processor-centric
  • Have gaps; not across whole of SoC
  • Usually cannot be used in-field or in-life
  • Not compatible with pre-silicon

Gap Inconsistent

Tape-out GA

Embedded World 2018 Commercial in Confidence

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SLIDE 19

Post-silicon with UltraSoC

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Complete post-silicon product § Integrated, coherent view across whole SoC § In-lab, field trial & in-life § ”Smart” data gathering § Synchronized HW, SW debug; multi-vendor BUT § Limited analytics, visualization § Not integrated with standard pre-silicon tools

Embedded World 2018 Commercial in Confidence

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SLIDE 20
  • A coherent architecture to debug, develop, optimize and secure
  • Full SoC visibility, HW & SW
  • Support all architectures: Freedom of IP selection
  • Real-time & non-intrusive
  • Advanced analytics & forensics
  • Power/Performance optimization
  • “in life” analytics & SLA compliance
  • Supports Functional Safety
  • Supports Bare Metal Security™
  • High-speed debug: USB or SerDes

UltraSoC: on-chip Analytics for SoC

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as a Whole

Embedded World 2018 Commercial in Confidence

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SLIDE 21

Actionable Insights across the Whole SoC

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Knowledge Information Data

UltraSoC enables full visibility of SoC Value UltraSoC delivers actionable insights With system-wide understanding From rich data across the whole SoC

Embedded World 2018 Commercial in Confidence

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SLIDE 22

Example problems UltraSoC solves

DDR3 Interconnect DFI-PHY DRAM controller Interconnect RAM DMA-1 Peripheral Interconnect USB MAC Turbo DSP Processor I$ D$

I TCM D TCM

Processor I$ D$

I TCM D TCM

DSP PHY DMA-2 DSP Timer Radio IF Radio IF FFT Interconnect Bus mon Bus mon Status mon Status mon Status mon Status mon Status mon UltraSoC Infrastructure Debug Hub UltraSoC IP Security Status mon Status mon Status mon

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BM BM SM SM SM SM SM SM SM SM

Debug Hub

UltraSoC IP

UltraSoC Infrastructure

Why do some DMA transfers take too long? Why is the CPU not performing as fast as expected? What is going on with my memory controller? Why does the system hang or deadlock on rare occasions? What is the mismatch between the host & the DSP? Why do I get data corruption? Why is that unauthorized process trying to access the keystore?

Embedded World 2018 Commercial in Confidence

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SLIDE 23

Examples of UltraSoC’s Analytics

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SLIDE 24

UltraSoC + Mentor Enable System Level View

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System Requirements Sub-System Design HW/SW Block Design HW/SW Implementation Module Integration Sub-System Integration System Acceptance

Validation

Validation

Validation

UltraSoC Provides System Level Analysis & Debug

System Memory Buffer Message Infrastructure DRAM Controller LCD Controller GPIO AXI Mon (xbm1) Virtual Console (vc1) AXI Comm. USB 2.0 Debug Hub Communicator ULPI to off-chip PHY Debug DMA (ddma1) LEDs & Switchs Custom Status Mon (sm1) Zynq SoC DRAM Controller SRAM SD Card etc SODIMM System Interconnect (AXI) UtraSoc Component ARM A9 (Bare) ARM A9 (Linux) CEVA-TL420 SoC USB AXI JTAG CTI AXI Proc. Analytic Module (pam1) CTI JTAG Proc. Analytic Module (jtm1) AXI Mon (xbm2) TAP TAP TAP TAP 5 pin 1149.1

Add UltraSoC IP Here ->

Post-Silicon Performance Analysis & Debug

  • Silicon “Bring-up”
  • Field Deployment

Embedded World 2018 Commercial in Confidence

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SLIDE 25

Mentor Graphics + UltraSoC

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Embedded World 2018 Commercial in Confidence

Expands & completes pre-silicon with very powerful tools that understand HW + SW “Verification Continuum” Complete post-silicon product § Integrated, coherent view across whole SoC § In-lab, field trial & in-life § ”Smart” data gathering § Synchronized HW, SW debug; multi-vendor BUT § Limited analytics, visualization § Not integrated with standard pre-silicon tools

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SLIDE 26

Mentor + UltraSoC = Synergy

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Complete Solution

  • From Design start, through emulation, tapeout, silicon to in-field + in-life
  • Consistent & compatible: whole SoC, HW + SW
  • Rich analytics & problem solving
  • Extend verification to post-silicon & in-field

Embedded World 2018 Commercial in Confidence

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SLIDE 27

Mentor + UltraSoC = Closed Loop

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Data Visual

  • ization

Analysis

Simulation Emulation Prototype Lab test Field trial In Life

Tape-out GA

Complete Solution

Embedded World 2018 Commercial in Confidence

In-product: Fix bugs Optimize Performance SLA reporting Feedback: Fix bugs in silicon or IP Value-engineering / cost-reduction

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SLIDE 28
  • UltraSoC has the only commercial development

environment for RISC-V

  • UltraSoC has RISC-V Run-control & Trace
  • FPGA demonstrator, Eclipse IDE

(gdb, gcc, openOCD) + commercial tools

  • Silicon proven
  • Partner with leading core vendors

RISC-V

28 Embedded World 2018 Commercial in Confidence

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SLIDE 29

RISC-V Demo System Architecture

  • Zynq FPGA platform
  • 2xARM
  • RISC-V

Rocket RV32 OR SiFive E51 OR Andes N25

  • custom logic
  • Demo shows:
  • Bus state
  • Traffic
  • Performance histogram
  • Memory
  • Processor control
  • Integrate with Veloce

Embedded World 2018 Commercial in Confidence

System Memory Buffer Message Infrastructure DRAM Controller LCD Controller GPIO AXI Mon (xbm1) Virtual Console (vc1) JTAG Comm. AXI Comm. USB 2.0 Debug Hub Communicator ULPI to off-chip PHY 5 pin 1149.1 Debug DMA (ddma1) LEDs & Switchs Custom Status Mon (sm1)

Zynq SoC

DRAM Controller SRAM SD Card etc SODIMM System Interconnect (AXI) ARM A9 (Bare) ARM A9 (Linux) RISC-V core SoC USB

AXI JTAG CTI

AXI Proc. Analytic Module (pam1)

CTI

JTAG Proc. Analytic Module (jtm1) AXI Mon (xbm2) Debug AXI- IF 1 1

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NB Other demos feature MIPS, CEVA, ARC, Xtensa etc

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SLIDE 30

RISC-V Foundation at Embedded World

  • Visit the RISC-V Foundation booth (Hall 3A, booth 3A-419)
  • Drinks will be served at the booth following today’s presentations.
  • Join the RISC-V Foundation scavenger hunt for a chance to win prizes

(visit booth for details)

  • To learn more, please visit: www.riscv.org

30 Embedded World 2018 Commercial in Confidence

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SLIDE 31

RISC-V Foundation at Embedded World

  • Check out the full RISC-V Class Agenda:
  • 9:30 - 10:00 – Running RTOS on RISC-V
  • 10:00 - 10:30 – RISC-V: Emulation and Rich, Non-intrusive Analytics Address Verification Complexity
  • 10:30 - 11:00 – Cycle Approximate Timing Simulation of RISC-V Processors
  • 11:30 - 12:00 – Securing RISC-V Machines Dynamically with Hardware-Enforced Metadata Policies
  • 12:00 - 12:30 – RISC-V ISA and Foundation Overview
  • 14:30 - 15:00 – A RISC V-based Open Hardware Platform for Wearable
  • 15:00 - 15:30 – A RISC-V Based Heterogeneous Cluster
  • 16:00 - 16:30 – Precisely Engineered RISC-V Embedded Processors in 30 Days
  • 16:30 - 17:00 – RISC-V in High Computing, Ultra-low-power, Programmable Circuits
  • 17:00 - 17:30 – Efficiency of the RISC-V ISA-level Custom Extension

31 Embedded World 2018 Commercial in Confidence

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SLIDE 32

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Contact details:

Rupert Baines

rupert.baines@ultrasoc.com www.ultrasoc.com

@UltraSoC

Russ Klein

russ_klein@mentor.com www.mentor.com

@Mentor_Graphics

Embedded World 2018 Commercial in Confidence