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https://www.youtube.com/watch?v=
Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM - - PowerPoint PPT Presentation
Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM - - PowerPoint PPT Presentation
Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM big.LITTLE Architectures in Dense Linear Algebra Sandra Cataln, Rafael Rodrguez- Luis Costero, Francisco D. Igual, Snchez, Enrique S. Quintana-Ort Katzalin Olcoz
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Task parallelism
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Contribution
Asymmetry-oblivious scheduler Asymmetry-aware DLA library +
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Contribution
Asymmetry-oblivious scheduler Asymmetry-aware DLA library +
Task parallelism Data parallelism
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Contribution
Asymmetry-oblivious scheduler Asymmetry-aware DLA library +
Task parallelism Data parallelism Virtual Cores
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Software execution models for ARM big.LITTLE
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Target architecture
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Execution Models
Cluster swithching mode
CPU Migration Global task scheduling
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Parallel execution of DLA operations
- n multi-threaded architectures
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A=UTU
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Runtime task scheduling of DLA
- perations
- Task scheduling for the Cholesky factorization
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Runtime task scheduling of DLA
- perations
- Task scheduling in heterogeneous architectures
– The runtime distinguishes between CPU and
GPU targets: OmpSs, StarPU, MAGMA, libflame
– Tasks assigned depending on target properties
and specific techniques are applied
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Runtime task scheduling of DLA
- perations
- Task scheduling in asymmetric architectures
– Asymmetry-concious runtime: Botlev-OmpSs – Critical-aware Task Scheduler policy – Each task is mapped to a single core
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Data parallel libraries of BLAS3 kernels
- Multi-threaded implementation of the BLAS-3
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Data parallel libraries of BLAS3 kernels
- Data-parallel libraries for asymmetric
architectures:
– Global Task Scheduling – Dynamic workload distribution between the
clusters
– Static workload distribution in a cluster – Specific loop strides for each type of core
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Retargeting existing task schedulers to asymmetric architectures
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Evaluation of conventional runtimes
- n AMPs
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Combining conventional runtimes with asymmetric libraries
- GTS model (inspired in CPUM)
– Virtual cores composed of 1A15 + 1A7 – Both cores are active simultaneously
- Parallelism:
– Task-level: symmetric runtime – Data-level: asymmetric library
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Combining conventional runtimes with asymmetric libraries
- Comparison with other approaches:
✔ Any conventional task scheduler will work
transparently with no special modifications
✔ Any improvement in the runtime will impact the
performance on an AMP
✔ Any improvement in the asymmetry-aware library
will impact the performace on an AMP
✗ Need of a tuned asymmetry-aware DLA library
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Experimental results
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Performance evaluation of the asymmetric BLIS
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Performance evaluation of the asymmetric BLIS
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Integration of the asymmetric BLIS in a conventional task scheduler
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Performance comparison versus asymmetry-aware task scheduler
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Conclusions
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In this work...
- Task-parallelism + Data-parallelism on AMPs
- Reuse of existing task schedulers.
- Competitive with asymmetry-aware schedulers
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