Real Chip Evaluation of a Low Power CGRA with Optimized Application - PowerPoint PPT Presentation

Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano Keio University, Japan International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2018), Toronto, Canada

Outline n Introduction n A CGRA Architecture n Three Types of Control 1. Pipeline Structure Control 2. Body Bias Control 3. Application Mapping n New Mapping Optimization Method n Real Chip Implementation n Experimental Results n Conclusion �

Importance of Low Power Consumption n Forthcoming n IoT devices n Wearable computing n Sensor network n Challenges n High performance n For image processing n Low Power Consumption n For long battery life �

SF-CGRAs: Straight-Forward Coarse-Grained Reconfigurable Arrays Permutation Network Permutation Network PE PE PE PE Pipeline Register Date Memory PE PE PE PE PE PE PE PE PE PE PE PE n Key features of straight-forward CGRAs n Pipelined PE array n Limited data flow direction n Less frequent reconfiguration n High energy efficiency �

VPCMA: Variable Pipelined Cool Mega Array [1] n PE array consists of PE PE PE PE � � � n 8 x 12 PEs PE PE PE PE n 7 pipeline registers Pipeline � � � n PE has Registers � � PE-Array � � n No Register file � � n No clock tree PE PE PE PE � � � n Pipeline register works in μ-controller 1. latch mode PE PE PE PE or � � � 2. bypass mode n μ-Controller Data Manipulator n Controls data transfer Data Memory data mem. ↔ PE array � [1] N.Ando , et al . "Variable pipeline structure for Coarse Grained Reconfigurable Array CMA." Field-Programmable Technology , 2016.

Pipeline Structure Control 3rd stage 4th PE Row Pipeline Register 2nd stage 3rd PE Row 2nd PE Row 1st stage 1st PE Row Number of Pipeline Stage Large Small Operating Frequency Throughput Glitch Propagation 6 Dynamic Power of Registers & Clock

Pipeline Structure Control 4th PE Row 2nd stage Pipeline Register 3rd PE Row 2nd PE Row 1st stage 1st PE Row Number of Pipeline Stage Large Small Operating Frequency Throughput Glitch Propagation 7 Dynamic Power of Registers & Clock

Body Bias Effects on SOTB n SOTB Technology n 65 nm n One of FD-SOI n Body Biasing Performance Decrease Enhancement of Static Power Reverse Bias Forward Bias Zero Bias n Tradeoff between leak power and performance �

Row-level Body Bias Control Probability of Leak Power Reduction Delay Time of PE for Each Opcode 4 Stage Pipeline 2 Stage Pipeline Delay time in case of SL no control Delay time in case of AND row-level control MULT Time Deadline ADD 9

How to map an application to the PE array? − − OR map Mapping Eval. OR n High Performance + × n Large Power + × << >> << >> Example of PE Array Application DFG n An app. is represented as a data flow graph (DFG) �� n Various Mappings exist

How to map an application to the PE array? − Mapping Eval. n Small Power n Low Performance OR map + × − OR << >> << + × >> Example of PE Array Application DFG n An app. is represented as a data flow graph (DFG) n Various Mappings exist ��

Complexity of Mapping Optimization ����(1(���.����(������� �(���-)� Interdependent �( �11�����������(2����2��(��� on each other �) ���2����)�2�������1 control NP-Complete Problem 3. Body Bias Voltage 2. Pipeline (BBV) for Each Row Structure (# of Rows)^(# of voltages) 128 patterns patterns Dynamic Static Power Power �� n Tradeoff between leak power and dynamic power

Related work 1. Performance & power optimization for CGRA[2] Considering VDD control n Optimization Priority: Performace > Power n 2. Body bias domain size exploration for CGRAs[3] Analysis of area overhead and power reduction effects n Not taking care of the dynamic power n 3. Pipeline & body bias optimization for CGRAs [4] Method using integer-linear-program n Assuming static mapping n [2] Gu, Jiangyuan, et al. "Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.” Design Automation Conference (ASP-DAC), 2017 22nd Asia and South Pacific . IEEE, 2017. [3] Y.Matsushita, “Body Bias Grain Size Exploration for a Coarse Grained Reconfigurable Accelerator”, Proc. of the 26th The International Conference on Field-Programmable Logic and Applications (FPL),2016. [4] T. Kojima, et al . “Optimization of body biasing for variable pipelined coarse-grained reconfigurable architectures”. IEICE Transactions on Information and Systems, Vol. E101-D,No. 6, June 2018. ��

Is optimizing only the power consumption enough? n Several requirements n Power Consumption n Performance (Operating Frequency) n Throughput n Multi-Objective Optimization brings users n A variety of choices Power n Balancing the tradeoffs �� Throughput Performance

Proposal: Use Multi-Objective Optimization n Non-dominated Sorting Genetic Algorithm-II (NSGA-II) n Multi-Objective Genetic Algorithm n In this work n 1-point crossover n Commonly-used probability [5] n 0.7 crossover probability n 0.3 mutation probability n 300 generations [5] L. Davis. “Adapting operator probabilities in genetic algorithms”. In Proceedings of the third �� international conference on Genetic algorithms, pp. 61–69, San Francisco, CA, USA, 1989. Morgan Kaufmann Publishers Inc.

Gene & Evaluation of Individuals ���������� DFG Mapping Pipeline Structure Routing Analyze Target Each Path Freq. Glitch ILP Solver Estimation for BBVs BBV for Degree of Static Total Wire Dynamic Each Row Parallelism Power Length Power Critical Path Delay Total �� Power

Gene & Evaluation of Individuals ���������� DFG Mapping Pipeline Structure • Dynamic power model • Proposed in [6] Routing Analyze • Considering glitch Target Each Path propagation Freq. • Based on results Glitch ILP Solver of real chip Estimation for BBVs measurements BBV for Degree of Static Total Wire Dynamic Each Row [6] T.Kojima, et al . “Glitch-aware Parallelism Power Length Power variable pipeline optimization for Critical CGRAs”. ReConFig2017, pp. 1–6, Dec 2017. Path Delay Total �� Power

Gene & Evaluation of Individuals ���������� DFG Mapping Pipeline Structure • An Integer Linear Program (ILP) Routing Analyze • Minimizes the static power Target Each Path • Considers timing constraints Freq. • Takes within 0.1 sec Glitch ILP Solver • The same method as proposed Estimation for BBVs in [4] BBV for Degree of Static Total Wire Dynamic Each Row [4] T. Kojima, et al . “Optimization of body Parallelism Power Length Power biasing for variable pipelined coarse-grained reconfigurable architectures”. IEICE Transactions Critical on Information and Systems, Vol. E101-D, Path Delay No. 6, June 2018. Total �� Power

An Implemented Real Chip “CCSOTB2” PE Array 3mm Body Bias Domains TCI domain1 1-5th PE Rows domain2 6th PE Row 6mm domain3 7th PE Row n CCSOTB2 domain4 8th PE Row n VPCMA Architecture domain5 other parts n SOTB 65nm Technology n 5 Body Bias Domains n Design: Verilog HDL n Synthesis: Synopsys Design Compiler �� n Place & Route: Synopsys IC Compiler

Preliminary Experiments Mother Board Zero Bias n Leak power of PE row is measured Artex-7 CCSOTB2 Chip n BBV: -0.8 ~ +0.4 V (step: 0.2 V) FPGA n Maximum Operating Freq. Experimental Environment n 30MHz n due to bottleneck in μ-controller ��

Benchmark Applications Name Description af 24bit alpha blender gray 24bit gray scale sepia 8bit sepia filter sf 24 bit sepia filter n 4 simple image processing application n Assuming 30MHz frequency ��

Proposed method vs. Black-Diamond n Black-Diamond [7] n does not support pipeline control nor body bias control n Static mapping regardless of user’s requirements n Combine with pipeline optimization[6] n Considering glitch effects [6] T.Kojima, et al . “Glitch-aware variable pipeline optimization for CGRAs”. ReConFig2017, pp. 1–6, Dec 2017. [7] V.Tunbunheng , et al . “Black-diamond: a retargetable compiler using graph with configuration bits for dynamically reconfigurable architectures”. In Proc. of The 14th SASIMI, pp. 412–419, 2007. ��

Mapping quality -0.4 V -0.4 V -0.4 V 0.0 V 0.0 V Black-Diamond with Proposed method pipeline optimization �� Difference of mapping results (gray application)

Mapping quality -0.2 V 0.0 V 0.0 V 0.0 V 0.0 V Black-Diamond with Proposed method pipeline optimization �� Difference of mapping results (af application)

Power reduction n For all applications, the total power is reduced n In average, 14.2 % reduction is achieved ��

Conclusion n A new optimization method based on a multi- objective genetic algorithm is proposed n Three controls are considered simultaneously 1. Pipeline structure control 2. Body bias control 3. Application mapping n Real chip experiments shows 14.2% power reduction ��