[PPT] - RAI: Securing Embedded Systems with Return Address Integrity Naif PowerPoint Presentation

SLIDE 1

μRAI: Securing Embedded Systems with Return Address Integrity

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1 2 3 4 5 6 Abraham A. Clements3,4,5 Saurabh Bagchi1,4 Mathias Payer2,5 Naif Saleh Almakhdhub1,4,5,6

Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. SAND-XXXX

SLIDE 2

Current State of Security

[1] https://www.wired.com/story/broadpwn-wi-fi-vulnerability-ios-android/ [2] https://keenlab.tencent.com/en/2020/01/02/exploiting-wifi-stack-on-tesla-model-s/ [3] https://www.securityweek.com/rise-ics-malware-how-industrial-security-threats-are-becoming-more-surgical

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[1] [2] [3]

Target:

Embedded and IoT devices Running Microcontroller Systems (MCUS)

Attack:

Control-flow Hijacking

SLIDE 3

MCUS Challenges

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Desktop MCUS

… … … … Code

Flash (code)

Stack … Heap … Data

RAM (Data)

… Stack … … … Heap … … Data … Code

Memory

0x08055555 0x08022222 0x08011111 0x08000000 0x08999555 0x08777222 0x08555111 0x08111000 0x08000000 0x02000000 0x02050000

 Large virtual memory (GBs)  Basic defenses (e.g., ASLR)  DEP  Small physical memory (MBs Flash, KBs RAM)  Basic defenses (e.g., ASLR)  Smaller code  DEP (Disabled  Fixable) Larger code

SLIDE 4

MCUS Defenses for Return Addresses (Conceptual)

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Security Runtime Overhead 10%

Usage Location Integrity

μRAI

Return Address Integrity + Low runtime overhead + No special hardware Limited Security Guarantees High Overhead

Shadow Stack + TEE Randomized Safe Stack Safe Stack + Software Fault Isolation Shadow Stack + MPU CFI

Special hardware required Without extra hardware

SLIDE 5

MCUS Defenses for Return Addresses (Related Work)

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Security Runtime Overhead 10%

Usage Location Integrity

μRAI

Return Address Integrity + Low runtime overhead + No special hardware Limited Security Guarantees High Overhead

EPOXY

(SafeStack) [S&P17]

CFI CaRE

(Shadow stack) [RAID17]

ACES

[SEC18]

Minion

[NDSS18]

SCFP

[EuroS&P18]

C-FLAT

[CCS16]

LiteHAX

[ICCAD18]

uXOM

[SEC19]

RECFISH

[ECRTS 2019]

μArmor

[EuroS&P19]

Special hardware required Without extra hardware

Symbiote

[RAID11]

SLIDE 6

Return Address Integrity (RAI)

Every attack requires corrupting a return addresses by overwriting it
Main limitation of defenses  return addresses are in writable memory
Example: Information hiding
Key solution is to prevent an attacker from corrupting return addresses.

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RAI Property:

Ensure the return address is never writable except by an authorized instruction.
Return addresses are never pushed to the stack or any writable memory by an adversary.

SLIDE 7

Threat Model & μRAI Protection

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Normal application

Func2 main Func3 Func1 Func6 Func4 Func7 Func5

Unprivileged Privileged

MPU, VTOR

Corrupt return address

r corrupt sensitive

Memory Mapped IO (MMIO) Corrupt return address

μRAI

Func2 main Func3 Func1 Func6 Func4 Func7 Func5 MPU, VTOR : Normal function : Callable within exception handler : MMIO : State register encoding : Software-Fault Isolation (SFI)

Reads from memory
Writes to memory
Knows the code layout
Targets backward-edges

SLIDE 8

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μRAI: Overview

State Register Read + eXecute Jump Table

Jump return_location1 Jump return_location2 …

1

Enforces the RAI property

3

Low runtime overhead

2

Protects exception handlers and privileged execution Exception handler software-fault isolation Relative jump target lookup routine

SLIDE 9

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μRAI: Overview

State Register Read + eXecute Jump Table

Jump return_location1 Jump return_location2 …

1

Enforces the RAI property

3

Low runtime overhead

2

Protects exception handlers and privileged execution Exception handler software-fault isolation Relative jump target lookup routine

SLIDE 10

μRAI and the State Register

State Register (SR):
Can be any general-purpose register  exclusively used by μRAI
Never spilled  cannot be overwritten through a memory corruption
Does not contain a return address  encoded values to resolve the return location
Example call graph:
Each edge  call
How encode SR?
An XOR chain

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Func2 Func1 main

SR SR SR SR

Func2 reads the SR to resolve the correct return location

SLIDE 11

μRAI: Terminology

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Address <Func2>: … … … … … … … … … … … … … … … …

Function Keys (FKs): Hard-coded keys used to encode the SR

SR[Recursive] SR[Encoded] C

SLIDE 12

μRAI: Terminology

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C

Function IDs (FIDs): Possible values of the SR for the function

SLIDE 13

μRAI: Terminology

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C

Function Lookup Table (FLT): List of FIDs for the function.

SLIDE 14

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C

Encode the SR and call Func2

SLIDE 15

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C key1 SR[Recursive] SR[Encoded]

Func2 reads the SR and executes the corresponding direct jump

SLIDE 16

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C key1 SR[Recursive] SR[Encoded]

Func2 returns correctly and the SR is decoded

SLIDE 17

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C

The previous SR value is restored

SLIDE 18

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … … … … … … … … … … … … … … … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

SR[Recursive] SR[Encoded] C

The same happens for other calls. Func1 can then return correctly

SLIDE 19

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μRAI: Overview

State Register Read + eXecute Jump Table

Jump return_location1 Jump return_location2 …

1

Enforces the RAI property

3

Low runtime overhead

2

Protects exception handlers and privileged execution Exception handler software-fault isolation Relative jump target lookup routine

SLIDE 20

μRAI: Enforce RAI for exception handlers

Exception handlers execute with privileges
Can disable the MPU  enable code injection
Can corrupt exception stack frame  break RAI property
Solution:
Apply SFI only to functions callable by exception handlers
Limit SFI overhead compared to full-SFI

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Func1 Func2 Func3 Func5 Func4 main Exception Handler Func6

MPU VTOR Safe region Privileged Software-Fault Isolation

SLIDE 21

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μRAI: Overview

State Register Read + eXecute Jump Table

Jump return_location1 Jump return_location2 …

1

Enforces the RAI property

3

Low runtime overhead

2

Protects exception handlers and privileged execution Exception handler software-fault isolation Relative jump target lookup routine

SLIDE 22

Target Lookup Routine (TLR)

How can we find the correct direct jump in the FLT efficiently?
Use a relative jump before the FLT
Resolve the correct return location efficiently regardless of FLT size

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Address<Func1>: … … … … … … … Jump PC+SR FID Return Target 1 Jump location1 2 Jump location2 3 Jump ERROR 4 Jump location4 5 Jump location5 Use SR as an index

f a jump table

Align the FLT  make SR = 4 Assume the correct return location is location4 Comparing all FID can be slow!

SLIDE 23

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μRAI: Overview

State Register Read + eXecute Jump Table

Jump return_location1 Jump return_location2 …

1

Enforces the RAI property

3

Low runtime overhead

2

Protects exception handlers and privileged execution Exception handler software-fault isolation Relative jump target lookup routine

SLIDE 24

Evaluation

Five MCUS applications on Cortex-M4:
PinLock
FatFs_uSD
FatFs_RAM
LCD_uSD
Animation
CoreMark benchmark[1]
Standard MCUS performance benchmark

[1] EEMBC, “Coremark - industry-standard benchmarks for embedded systems,” http://www.eembc.org/coremark

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SLIDE 25

RX Memory

Security Evaluation Using PinLock: Unlock The Lock

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… … … … … …

RW Memory

buffer … … … … … …

RW Memory

ptr … … … … … …

RW Memory

buff

Jump Table

Jump return_location1 …

Buffer overflow Arbitrary write Stack pivot

buffer No return address to write to…

SP SP

Sensitive MMIO and Safe region Privileged

State Register

 μRAI prevents all control-flow hijacking attack scenarios targeting return addresses

No return address to pop from the stack No return address to

verflow…

SLIDE 26

Performance results

Requiring full-SFI results in high overhead  average of 130.5%
μRAI results in low overhead  average of 0.1%

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SLIDE 27

μRAI: Conclusion

Control-flow hijacking on MCUS is a threat
μRAI secures MCUS against control-flow hijacking
Enforces the RAI property for MCUS  protects backward edges
Complemented with type-based CFI  end-to-end code pointer protection
Presents a portable encoding scheme
Does not require special hardware features (only a register and an MPU)
Applicable to other systems
Low runtime overhead

https://github.com/embedded-sec/uRAI

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SLIDE 28

Backup Slides

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SLIDE 29

Challenge: Path Explosion

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Func3 Func1 Func2 main

SR[Rec] SR[Enc] [ ] SR[Rec] SR[Enc] SR[Rec] SR[Enc] SR[Rec] SR[Enc] SR[Rec] SR[Enc] [ ] SR[Rec] SR[Enc] SR[Rec] SR[Enc] [ ] SR[Rec] SR[Enc]

Func3 has 2 call sites
FLT is size is 4!

SLIDE 30

Path Explosion Solution: Segmentation

State register segmentation
Functions only use the bits in their assigned segment.

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Recursion counter (Higher N bits) Encoded value (Lower 32-N bits) Segment 1

…

Segment K Segment M … Segment 2 Segment 1

SLIDE 31

Path Explosion Solution: Segmentation

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Func3 Func1 Func2 main

SR[Rec] SR[Enc2] SR[Enc1] [ SR[Rec] SR[Enc2] SR[Enc1] SR[Rec] SR[Enc2] SR[Enc1] SR[Rec] SR[Enc2] SR[Enc1] SR[Rec] SR[Enc2] SR[Enc1] [ ] SR[Rec] SR[Enc2] SR[Enc1] SR[Rec] SR[Enc2] SR[Enc1] [ ] Not used SR[Rec] SR[Enc2] SR[Enc1] Not used

Segmentation reduces

FLT from 4 to 2

SLIDE 32

μRAI: Scalability

What if no more values can be found for the SR?
Solution:
Partition the call graph if no solution is found
Entering a new partition

Save and reset the SR to a privileged safe region

Returning to a previous partition

 Restore the SR

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Func1 Func2 Func3 Func5 Func4 main Exception Handler Func6

Safe Region Privileged

SLIDE 33

Memory results

Moderate overhead for large applications

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Average 15.2% Average FLT + Instrmnt. 34.6% EH-SFI 9.5% Type-CFI 10%

SLIDE 34

μRAI vs. backward edge Type-based CFI

[1] N. Carlini, A. Barresi, M. Payer, D. Wagner, and T. R. Gross, “Controlflow bending: On the effectiveness of control-flow

integrity,” in USENIX SEC15

161–176

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App Type-based CFI Target Set Max. Ave. PinLock 8 3 FatFs_uSD 94 21 FatFs_RAM 94 27 LCD_uSD 49 11 Animation 49 11 CoreMark 52 12

Overall Average 58 14

μRAI eliminates the remaining attack surface for control-flow bending attacks[1]

SLIDE 35

Store Instructions Protected with EH-SFI

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App # of Store instruction

Static Total (Static/Total)% Dynamic

PinLock 56 516 10.9 7 FatFs_uSD 99 1,802 5.5 906K FatFs_RAM 7 1,116 0.6 7 LCD_uSD 99 2,814 3.5 48K Animation 99 2,760 3.6 66K CoreMark 56 1,024 5.5 7

SLIDE 36

SR Layout

The SR has two parts:
ENC: Encoded value
REC: Recursion counter

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SR[Rec] SR[Enc] SR[Rec] SR[Enc] SR[Rec] SR[Enc] SR[Rec] SR[Enc]

Func3 main

Cannot use XOR with recursion
Collision occurs with existing values Func1

before the call after return If  recursion

SLIDE 37

μRAI: Transformation

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Address <Func1>: … SR[Enc] = SR[Enc] key1 … Call Func2 Func1_1 SR[Enc] = SR[Enc] key1 … … … SR[Enc] = SR[Enc] key2 … Call Func2 Func1_2 SR[Enc] = SR[Enc] key2 … … Function ID (FID) Return Target C Jump return_location1 ELSE Jump ERROR Address <Func2>: … SR[Rec]++ … Call Func2 Func2_1 SR[Rec]-- … … … IF SR[Rec] > 0 … Jump Func2_1 … ELSE … … Function ID (FID) Return Target C key1 ⊕ Jump Func1_1 C key2 ⊕ Jump Func1_2 ELSE Jump ERROR

If recursive  use a counter (recursion is discouraged in MCUS)

SR[Rec] SR[Enc] C

SLIDE 38

SR Encoding Illustration

Consider the following call graph with the SR initialized to a value = C
Each edge  call
XOR before the call and after returning with hardcoded keys
An edge is walked  XOR the SR

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SR SR SR C SR SR SR SR

Func2 main Func3

XORing again after returning  restores the previous SR

SLIDE 39

μRAI’s Overview

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LLVM Source code

μRAI

Call Graph Analyzer Generates caller/callees for each function Encoder Generates function keys and encodes SR Instrumentation μRAI binary LLVM IR

SLIDE 40

μRAI: Workflow

Generates caller/callee list.
Sets the minimum possible FLT.
Example: Func5 is called from

4 locations → Min. FLT >= 4

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Func1 Func2 Func3 Func5 Func4

2 2 4 3 Function

Min. FLT

DFS FLT Segmented FLT Func1

Func2
Func3

4 Func4 3 Func5 4

Call Graph Analyzer Encoder Instrumentation

SLIDE 41

μRAI: Workflow

Performs Depth First Search (DFS) on

the call graph to generate initial FLT

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Call Graph Analyzer Encoder Instrumentation

Function

Min. FLT

DFS FLT Segmented FLT Func1

Func2
Func3

4 4 Func4 3 12 Func5 4 16

Func1 Func2 Func3 Func5 Func4

2 2 4 3

SLIDE 42

μRAI: Workflow

Performs Depth First Search (DFS) on

the call graph to generate initial FLT

Configures the SR segment size to

reduce memory overhead

Generates FKs/FIDs

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Call Graph Analyzer Encoder Instrumentation

Function

Min. FLT

DFS FLT Segmented FLT Func1

Func2
Func3

4 4 4 Func4 3 12 3 Func5 4 16 4

Func1 Func2 Func3 Func5 Func4

2 2 4 3 Use first SR segment Use second SR segment

SLIDE 43

μRAI: Workflow

Instruments call sites with

encoding/decoding instructions

Remove any return instruction or uses
f the SR
Example: POP{PC}, PUSH{SR}
Instruments Target Lookup Routine (TLR) and FLT

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Call Graph Analyzer Encoder Instrumentation Address <Func1>: … SR = SR function_key … Call Func2 … SR = SR function_key … TLR: Execute the instruction where the FID = SR FID Return Target 1 Jump location1 2 Jump location2 … …

SLIDE 44

Microcontroller Systems (MCUS)

Embedded systems and IoT run on Microcontroller systems (MCUS)
MCUS:
Run a single static binary application directly on hardware
Can be with/without an lightweight OS (bare-metal)
Direct access to peripherals and processor
Can be standalone device or part of larger system
Advanced hardware features are not commonly available
Example: Trusted Execution Environment (TEE)
Examples:
WiFi System on Chip
Cyber-physical systems
UAVs

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SLIDE 45

Security Evaluation Using PinLock

Attacker tries to unlock the lock using a vulnerability in rx_from_uart
Attacker can read, write to anywhere in memory
Attacker knows the entire code layout
Even the current instance of the firmware

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Attack Prevented Buffer overflow  Arbitrary write  Stack pivot 

μRAI prevents all control-flow hijacking attack scenarios targeting return addresses

SLIDE 46

MCUS Challenges

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Desktop MCUS

… … … … …

Flash (code)

… … … … …

RAM (Data)

… Stack … … … Heap … … Data … Code

Memory

Stack Heap Code Data

0x08055555 0x08022222 0x08011111 0x08000000 0x08999555 0x08777222 0x08555111 0x08111000 0x08000000 0x02000000 0x02050000

 Virtual memory (MMU)  Large Memory (GB)  ASLR  Stack cookies  DEP  Special HW features (e.g., TEE)  Physical Memory (MPU)  Small Memory (MBs Flash, KBs RAM)  ASLR  Stack cookies (Inapplicable, or have limited security) DEP (Disabled  Fixable)  Smaller Code  Special HW features (Not commonly available)

SLIDE 47

Control-Flow Hijacking

Attacker gains arbitrary execution
Originates from memory corruption vulnerability
Code pointers:
Forward edges
Backward edges

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Normal application

… … … … … … …

Data (RW)

Code Pointer ptr … Func1 Func2 Func3 Func4 Func5 …

Code (RX)

SLIDE 48

Forward edges:
Function pointers
Virtual calls (C++)
Control-Flow Integrity (CFI):
Calculates target set statically
Reduces target set significantly
Backward edges:
Return addresses
Current mechanisms:
Limited security guarantees
Example: Large target set for CFI
High runtime overhead
Require special hardware

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Control-Flow Hijacking

f_ptr() Func1 Calls to Func1

Effective for MCUS 

SLIDE 49

Forward edges:
Function pointers
Virtual calls (C++)
Control-Flow Integrity (CFI):
Calculates target set statically
Reduces target set significantly
Backward edges:
Return addresses
Current techniques:
Limited security guarantees
Example: Large target set for CFI
High runtime overhead
Require special hardware

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Control-Flow Hijacking

f_ptr() Func1 Calls to Func1

Control-flow hijacking attacks on

backward-edges remain a threat.

Example: Return Oriented

Programming (ROP)

Effective for MCUS 

SLIDE 50

Control-flow hijacking defenses

Great effort has been done by research community to protect the IoT.
TyTan[DAC15], TrustLite[EurSys14], C-FLAT [CCS16], nesCheck[AsiaCCS17],

SCFP[EuroS&P18], LiteHAX[ICCAD18], CFI CaRE [RAID17], ACES[SEC18], MINION [NDSS18], EPOXY [S&P17]

Unfortunately, current defenses suffer from one of the following:

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Limitation Example of a Defense Mechanism Information disclosure Randomization Only limit the attack surface CFI (large target set) Require extra hardware Shadow stack High overhead Memory safety

SLIDE 51

Normal Application

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foo Func1 Func2 Func4 Func3 Func5 main … … … … buff … … …

Stack (RW Memory)

Return address *ptr_at_foo … Func1 Func2 Func3 Func4 Func5 system

Code (RX Memory)

system

Sample call graph

Func6

SLIDE 52

Usage Defenses: Control-Flow Integrity (CFI)

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foo Func1 Func2 Func4 Func3 Func5 main … … … … buff … … …

Stack (RW Memory)

Return address *ptr_at_foo … Func1 Func2 Func3 Func4 Func5 system

Code (RX Memory)

system

Sample call graph

Func6

Defense:

SLIDE 53

Location Defense: Randomization

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foo Func1 Func2 Func4 Func3 Func5 main … … … … buff … … …

Stack (RW Memory)

Return address *ptr_at_foo Func1 Func2 Func3 Func4 Func5 Func6 system

Code (RX Memory)

system

Sample call graph

Func6

Defense:

CFI

Return address Return address

??? Disclose the layout

Func5 Func2 Func4 system Func3 Func1 Func6

SLIDE 54

Integrity Defenses: Shadow Stack

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foo Func1 Func2 Func4 Func3 Func5 main … … … … buff … … …

Stack (RW Memory)

Return address *ptr_at_foo … Func1 Func2 Func3 Func4 Func5 system

Code (RX Memory)

system

Sample call graph

Func6

Defense:

CFI Randomizatjon

… Return address …

Shadow Stack (Hardware Isolation)

System keeps 2 copies
f return address
Attacker cannot corrupt

shadow stack

Different return

addresses  Attack detected

SLIDE 55

Integrity Defenses: Shadow Stack

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foo Func1 Func2 Func4 Func3 Func5 main … … … … buff … … …

Stack (RW Memory)

Return address *ptr_at_foo … Func1 Func2 Func3 Func4 Func5 system

Code (RX Memory)

system

Sample call graph

Func6

Defense:

CFI Randomizatjon Shadow stack

… Return address …

Shadow Stack (Hardware Isolation)

TEE not available
High overhead

SLIDE 56

State Register Layout

SR layout:

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Recursion counter (Higher N bits) Encoded value (Lower 32-N bits)

SLIDE 57

μRAI Protection

Attacker:
Has arbitrary write and read vulnerability
Knows the code layout, even the current instance of the firmware
Targets backward edges.
μRAI is complemented with DEP and type-based CFI for forward edge.

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Normal application μRAI

… … … … … … … … …

Stack

Return address ptr … … … … … … … … …

Stack

ptr SR = C (some value) ????

SLIDE 58

TLR with Segmentation

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Address Func1: … … … Genral_Register = SR[Segment2] … Jump PC+General_Register

FID Return Target 1 Jump location1 2 Jump location2 3 Jump ERROR 4 Jump location4 5 Jump location5 Func1 uses segment 1 Let SR = 0x00005FFF

Recursion counter (Higher 8 bits) Encoded value (Lower 32-N bits) Segment 2 (12 bits) Segment 1 (12 bits)

Shift by segmentation

SLIDE 59

SR Encoding

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Func3 Func1 Func2 main

SR SR SR SR SR C SR SR SR SR

Xor again after returning Xor is the inverse of itself