SLIDE 1
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2-21-2014 Zach Lasiuk 2
Overview
Courtesy of of E. Hazen
FPGA instruction
Pulse Injector Board 2-21-2014 Zach Lasiuk 1 Overview FPGA - - PowerPoint PPT Presentation
Pulse Injector Board 2-21-2014 Zach Lasiuk 1 Overview FPGA - - PowerPoint PPT Presentation
Pulse Injector Board 2-21-2014 Zach Lasiuk 1 Overview FPGA instruction Courtesy of of E. Hazen 2-21-2014 Zach Lasiuk 2 Board Layout DAC Power I2C BUS Buffer (Pulse Height) 3.3V FPGA signals Mezz Card Connectors Pulse Generating
SLIDE 2
SLIDE 3
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FPGA signals Inverters
(Pulse Triggers)
GPIO Expander
(slow, fixed pattern)
I2C BUS Buffer DAC
(Pulse Height)
Power
3.3V
Mezz Card Connectors Pulse Generating Sections
Board Layout
SLIDE 4
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AND gate Voltage Divider *Since the voltage divider circuit is
inverted, we get a very small 'negative' pulse.
*The GPIO and trigger signals must
both be on for a pulse to be generated.
Low-Pass filter *One trigger signal can activate/control
four pulses.
Pulse Generating Close-Up
*Charge sent to Mezz Card
varies from 0-100fC
SLIDE 5
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*Three different types of Mezz Cards