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Project: IEEE P802.15 Working Group for Wireless Personal Area - - PowerPoint PPT Presentation

July 9, 2006 doc.: IEEE 802.15-0760-01-003c Project: IEEE P802.15 Working Group for Wireless Personal Area Networks ( etworks (WPANs WPANs) ) Project: IEEE P802.15 Working Group for Wireless Personal Area N Submission Title: [TensorCom


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SLIDE 1

July 9, 2006

Ismail Lakkis, Tensorcom Slide 1

doc.: IEEE 802.15-0760-01-003c

Submission

Project: IEEE P802.15 Working Group for Wireless Personal Area N Project: IEEE P802.15 Working Group for Wireless Personal Area Networks ( etworks (WPANs WPANs) )

Submission Title: [TensorCom Physical Layer Proposal] Date Submitted: [ 9 July, 2007] Source: [Ismail Lakkis] Company [Tensorcom] Address [10875 Rancho Bernardo Rd #108, San Diego, CA, USA] Voice:[858-676-0200], FAX: [858-676-0300], E-Mail:[ ilakkis@tensorcom.com] Re: [This submission is in response to the TG3C call for Proposals (IEEE P802.15-07-0586-02-003c)] Abstract: [This document describes the Tensorcom physical layer proposal for IEEE 802.15 TG3C.] Purpose: [For considereation and discussion by IEEE 802.15 TG3C.] Notice: This document has been prepared to assist the IEEE P802.15. It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein. Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P802.15.

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SLIDE 2

July 9, 2006

Ismail Lakkis, Tensorcom Slide 2

doc.: IEEE 802.15-0760-01-003c

Submission

TensorCom Physical Layer Proposal Dual-Mode Single Carrier / OFDM

Ismail Lakkis Tensorcom 10875 Rancho Bernardo Rd, #108 San Diego, CA, 92127 July 09, 2007

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SLIDE 3

July 9, 2006

Ismail Lakkis, Tensorcom Slide 3

doc.: IEEE 802.15-0760-01-003c

Submission

Outline

! PHY key features ! Channelization ! Common Preamble ! Unified Frame format ! Single Carrier Mode ! OFDM Mode ! Selected responses to the selection criteria ! Summary

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SLIDE 4

July 9, 2006

Ismail Lakkis, Tensorcom Slide 4

doc.: IEEE 802.15-0760-01-003c

Submission

PHY Key Features

! Dual-mode SC (Single Carrier) / OFDM for different classes of devices and different applications; ! Low-complexity interoperability common m ode for interoperability between different devices/ networks; ! Unified common frame format enabling a single HW supporting SC / OFDM; ! Link Adaptation & Unequal Error Protection via low – complexity Structured Turbo LDPC / RS; ! Balanced Channelization with multiple XTAL support.

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SLIDE 5

July 9, 2006

Ismail Lakkis, Tensorcom Slide 5

doc.: IEEE 802.15-0760-01-003c

Submission

Channelization

! Desired Features ! Band Plan ! Direct conversion PLL Reference Diagram ! Heterodyne PLL Reference Diagram: Variable IF ! Heterodyne PLL Reference Diagram: Fixed IF

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SLIDE 6

July 9, 2006

Ismail Lakkis, Tensorcom Slide 6

doc.: IEEE 802.15-0760-01-003c

Submission

Channelization Desired Features

! Use “free spectrums” of Japan, USA, Korea & EU ! Support for 4 channels in the available spectrum ! Channel Separation in the order of 2 GHz ! Single/ Dual integer PLL that generates all necessary frequencies using direct synthesis ! Support of multiple PLL architectures (Direct conversion, double conversion) ! High Frequency Dividers should be in power of 2 : low-frequency dividers can be programmable ! Support of multiple crystals including at least one cell crystal &

  • ne high frequency crystal
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SLIDE 7

July 9, 2006

Ismail Lakkis, Tensorcom Slide 7

doc.: IEEE 802.15-0760-01-003c

Submission

Channelization

3 4 2 1

! Support Cell phone XTAL: 15 MHz, 18 MHz, 19.2 MHz & 24 MHz & Other High frequency XTALs: 22.5, 27, 30, 33.75, 36, 45, 54MHz, … ! Balanced margins to 57/ 66 GHz & Good roll-off factor ! Supports Multiple PLL Architectures even with the Cell phone XTAL ! Dual PLL: High frequency PLL that generates carrier frequencies ! Low frequency PLL that generates the ADC/ DAC & ASIC frequencies

0.25 1728 65.880 64.800 63.720 4 1728 1728 1728

3 dB BW (MHz)

63.720 61.560 59.400

High Freq. (GHz)

0.25 62.640 61.560 3 2 1

Channel Number

0.25 60.480 59.400 0.25 58.320 57.240

Roll-Off Factor Center Freq. (GHz) Low Freq. (GHz) 240 MHz 120 MHz 1296 MHz 1728 MHz 2160 MHz 57 58 59 60 61 62 63 64 65 66 fGHz

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SLIDE 8

July 9, 2006

Ismail Lakkis, Tensorcom Slide 8

doc.: IEEE 802.15-0760-01-003c

Submission

Direct Conversion PLL Reference Diagram

5 2×3×5 1 3 32 1 675.00 675.00 2.02500 22.5 64.800 5 29 1 3 32 1 652.50 652.50 1.95750 22.5 62.640 5 2×2×7 1 3 32 1 630.00 630.00 1.89000 22.5 60.480 5 3×3×3 1 3 32 1 607.50 607.50 1.82250 22.5 58.320 4.050 3.915 3.780 3.645 8.100 7.830 7.560 7.290 4.050 3.915 3.780 3.645

fQ(GHz)

1 3×3×3 1 5 16 1 729 729 27 58.320 1 2×2×7 1 5 16 1 756 756 27 60.480 1 29 1 5 16 1 783 783 27 62.640 1 2×3×5 1 5 16 1 810 810 27 64.800 1 3×3×3 5 3 8 1 486 2430 18 58.320 1 2×2×7 5 3 8 1 504 2520 18 60.480 1 29 5 3 8 1 522 2610 18 62.640 1 2×3×5 5 3 8 1 540 2700 18 64.800 2×3 ×5 29 2×2 ×7 3×3 ×3

M

3 3 3 3

N

1 1 1 1

R1

16 16 16 16

P

3 3 3 3

Q

450 435 420 405

fM (MHz)

5 1350 15 64.800 5 1305 15 62.640 15 15

fX (MHz)

5 1260 60.480 5 1215 58.320

R2 fN (MHz) fc (GHz)

÷ 64x3 XTAL Oscillator Phase Detector LPF VCO ÷ P

fX fc fM fN

÷ N ÷ M Phase Detector LPF VCO

Example: fADC = 3456 MHz

÷ 512 ÷ R1 ÷ R2 ADC/DAC options: 1728 MHz 2592 MHz 3456 MHz ÷ 128 ÷ Q

fQ

÷ 128x3

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SLIDE 9

July 9, 2006

Ismail Lakkis, Tensorcom Slide 9

doc.: IEEE 802.15-0760-01-003c

Submission

Heterodyne PLL Reference Diagram: Variable IF

5 2x3x5 1 64 2 1 450 450 7.200 28.800 15 64.800 5 29 1 64 2 1 435 435 6.960 27.840 15 62.640 5 2x2x7 1 64 2 1 420 420 6.720 26.880 15 60.480 5 3x3x3 1 64 2 1 405 405 6.480 25.920 15 58.320 25.920 25.056 24.192 23.328 43.200 41.760 40.320 38.880 25.920 25.056 24.192 23.328

fs (GHz)

810 783 756 729 675.00 652.50 630.00 607.50 1620 1566 1512 1458

fN (MHz)

2×3×5 29 2×2×7 3×3×3 2×3 ×5 29 2×2 ×7 3×3 ×3 2×3×5 29 2×2×7 3×3×3

M

1 1 1 1 1 1 1 1 3 3 3 3

N

1 16 2 1 540 12.960 18 64.800 1 16 2 1 522 12.528 18 62.640 1 16 2 1 504 12.096 18 60.480 1 16 2 1 486 11.664 18 58.320 1 1 1 1 1 1 1 1

R1

2 2 2 2 1 1 1 1

P

32 32 32 32 64 64 64 64

Q

810 783 756 729 675.00 652.50 630.00 607.50

fM(MHz)

1 11.664 27 58.320 1 12.096 27 60.480 1 12.528 27 62.640 5 21.600 22.5 64.800 5 20.880 22.5 62.640 1 12.960 27 64.800 22.5 22.5

fX(MHz)

5 20.160 60.480 5 19.440 58.320

R2 fIF (GHz) fc (GHz)

÷ 64x9

XTAL Oscillator Phase Detector LPF VCO ÷ Q

fX fRF-Mixer

× P

fM fS

÷ N ÷ M Phase Detector LPF VCO

Example: fADC = 3456 MHz

÷ R1 ÷ R2

÷ 2/4

fIF-Mixer I Q

%4 " fIF ~ 6-7 GHz %2 " fIF ~ 11-13 GHz P = 1 " fIF ~ 19-21 GHz ADC/DAC options: 1728 MHz 2592 MHz 3456 MHz

fN

÷ 16x3x3 ÷ 128 ÷ 4x3x3x5

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SLIDE 10

July 9, 2006

Ismail Lakkis, Tensorcom Slide 10

doc.: IEEE 802.15-0760-01-003c

Submission

Heterodyne PLL Reference Diagram: Fixed IF

1809 1161 837 459 877.50 562.50 202.50 517.50 2412 2322 2232 2142 1170 1125 1080 1035

fN(MHz)

67 43 31 17 13 5 3 23 67 43 31 17 2x13 5x5 2x2x2x3 23

M

1 5 3 3 16 1 1170 3510 8.640 56.160 15 64.800 1 5 3 3 16 1 1125 3375 8.640 54.000 15 62.640 1 5 3 3 16 1 1080 3240 8.640 51.840 15 60.480 1 5 3 3 16 1 1035 3105 8.640 49.680 15 58.320 57.888 55.728 53.568 51.408 56.160 54.000 51.840 49.680 57.888 55.728 53.568 51.408

fRF (GHz)

3618 3483 3348 3213 1755.00 1687.50 1620.00 1552.50 7236 6966 6696 6426

fQ (MHz)

4 4 4 4 5 5 5 5 4 4 4 4

L

1 1 1 1 3 5 3 1 2 3 4 7

N

1 3 8 1 1206 6.912 18 64.800 1 3 8 1 774 6.912 18 62.640 1 3 8 1 558 6.912 18 60.480 1 3 8 1 306 6.912 18 58.320 1 1 1 1 1 1 1 1

R1

16 16 16 16 32 32 32 32

P

2 3 4 7 2 3 8 3

Q

1809 1161 837 459 292.50 112.50 67.50 517.50

fM(MHz)

1 6.912 27 58.320 1 6.912 27 60.480 1 6.912 27 62.640 1 8.640 22.5 64.800 1 8.640 22.5 62.640 1 6.912 27 64.800 22.5 22.5

fX(MHz)

1 8.640 60.480 1 8.640 58.320

R2

fIF (GHz) fc (GHz)

÷ 64x3

XTAL Oscillator Phase Detector LPF VCO

fX fM fRF

÷ N ÷ M Phase Detector LPF VCO

fADC

÷ R1 ÷ R2 ADC/DAC options: 1728 MHz 2592 MHz 3456 MHz

fN

÷ 16x3x3 ÷ 128

÷ L

fIF

÷ Q

fQ

÷ P

÷ 4x3x3x5

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SLIDE 11

July 9, 2006

Ismail Lakkis, Tensorcom Slide 11

doc.: IEEE 802.15-0760-01-003c

Submission

Common Mode

! Comm on Mode Highlights ! Preamble Structure & Frame Format ! Rate, Timing & Frame Related Parameters ! Transmitter Reference Diagram ! Spreading Codes & Properties ! The Modulator & Mapper ! The Reed Solomon FEC ! The Scram bler ! The Fram e & Header Check Sequences ! The Pulse Shaper

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SLIDE 12

July 9, 2006

Ismail Lakkis, Tensorcom Slide 12

doc.: IEEE 802.15-0760-01-003c

Submission

Common Mode Highlights

! Definition: Common Mode (CM) is a Base Rate (BR) Mode that is mandatory for all devices ! Usage: CM is used for beaconing, signaling and for BR data packets ! Common mode: necessary for interoperability between different devices & different networks ! Modulation: Golay symbols with chip level π/ 2-DBPSK ! Pulse Shaping: left to the implementer

! Example 1: GMSK or Linearized GMSK pulse with BT= 0.5 (recommended); ! Example 2: Square-root raised cosine with roll-off= 0.25 with clipping / lifting; ! Example 3: Square-root raised cosine with roll-off= 0.25 without clipping

! Coding: Shortened Reed-Solomon from RS(255,239) ! Spreading Codes:

! length 128 codes (a128 & b128) used for SYNC & SFD fields ! length 256 codes (a256 & b256) used for CES ! length 064 codes (a064 & b064) used for Header and data

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SLIDE 13

July 9, 2006

Ismail Lakkis, Tensorcom Slide 13

doc.: IEEE 802.15-0760-01-003c

Submission

! Long pream ble is the default preamble; ! PNC switch from long preamble to short preamble upon Device request (implicit or explicit) ! Header & PSDU are spread using Golay codes a64 & b64. Each symbol carries 2 bits of information

PLCP Preamble PLCP Header PSDU Packet/Frame Sync Sequence (Long Preamble: 30 Codes, Short Preamble: 8 Codes) SFD Start Frame Delimiter CES Channel Estimation Sequence

a128 a128 a128

  • a128

a256 a128

  • a128

aCP Long : Tpreamble = 2.963 µs Short: Tpreamble = 1.333 µs 128 aCP 128 b256 bCP bCP ±a64 ±b64 64 chips ~ 37ns aN & bN are a complementary Golay codes pair of length N

Preamble Structure & Frame Format

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SLIDE 14

July 9, 2006

Ismail Lakkis, Tensorcom Slide 14

doc.: IEEE 802.15-0760-01-003c

Submission

  • MSps

= Mega Symbols per second

  • Mbps

= Mega bits per second

  • FEC

= RS(240,224), Rate = 224/240 = 0.933

Chip Rate Modulation Spreading FEC Base Rate Bits per Base Date Rate Manatory or Rchip : MHz Scheme Length: L Rate MSps Symbol Mbps Optional 1728 π/ 2- BPSK/ GMSK 64 0.933 27 2 50.400 Mandatory

Common Mode: PSDU Rate-Dependent Parameters

Parameter Unit R c MHz T c ns N psym Chips T psym ns N cesym Chips T cesym ns N dsym Chips T dsym ns N cRS Chips T RSblk µs Data symbol length (chips) Data symbol duration value 1728 0.579

Common Mode: Timing-Related Parameters

128 74.074 256 148.148 64 37.037 1856 1.074 Reed Solomon block length (chips) Reed Solomon block duration CES symbol duration CES symbol length (chips) Preamble symbol duration Preamble symbol length (chips) Chip duration Chip rate Description

PSDU Rate & Timing Parameters

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SLIDE 15

July 9, 2006

Ismail Lakkis, Tensorcom Slide 15

doc.: IEEE 802.15-0760-01-003c

Submission

Parameter Unit Ns y nc Default mode: 30 Fast mode: 8 a128 Ts y nc Default mode: 2.222 Fast mode: 0.593 µs Ns fd a128 Ts fd µs Nc es a256/ b256 Tc es µs Npre Default mode: 40 Burst mode: 18 128 chips symbols Tpre Default mode: 2.963 Burst mode: 1.333 µs Nphdr a64/b64 Tphdr µs Nm hdr a64/b64 Tm hdr µs Nc hdr a64/ b64 Tc hdr µs Nhdr a64/ b64 Thdr µs NRSblk RS blocks Npad

  • ct et s

Nfram e 128 chips symbols Tfram e µs Nc pac k et chips 0.593 Duration of the channel estimation sequence Number of symbols in the frame sync sequence Number of symbols in the PHY header Duration of the PHY header Number of equivalent symbols in the PLCP preamble Duration of the PLCP preamble Number of Reed Solomon Blocks in the frame Duration of frame header Number of symbols in the MAC header Duration of the MAC header Number of chips in the packet Number of symbols in the frame Duration of the frame Number of zero pad octets Number of symbols in the packet sync sequence Duration of the packet sync sequence

Common Mode: Frame-Related Parameters

Description Value 2 Number of symbols in the channel estimation sequence 0.148 4 Duration of the frame sync sequence 40 0.741 80 1.481 80 Number of symbols in the header HCS & RSP Number of symbols in the frame header 200 1.481 Duration of the header HCS & RSP 3.704 NRSblk× 240 Nfram e×Tds y m Nfram e× 8× 32 224× NRSblk - (LENGTH + 4) ceil[ (LENGTH + 4)/224]

PSDU Frame Dependent Parameters

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SLIDE 16

July 9, 2006

Ismail Lakkis, Tensorcom Slide 16

doc.: IEEE 802.15-0760-01-003c

Submission

Scrambled & RS Encoded PLCP Header (200b) MAC Header 10 octets Compute HCS Scramble Shortened RS(25,17) RS(24,16) Parity Bits 8 octets Scrambled HCS 2 octets Scrambled MAC Header 10 octets PHY Header 5 octets Append

HCS (16b) MAC_HDR/HCS (96b)

PHY Header 5 octets

Scrambled MAC_HDR (80b) Scrambled HCS (16b) PHY_HDR (40b) MAC_HDR (80b) PHY_HDR (40b)

MAC HDR 10 Octets Frame body 0: 65535 Octets CRC 4 Octets RS(255,239) Scramble Append Golay Symbol Mapper Preamble Insertion π/2-DBPSK/GMSK Modulator Optional Pulse Shaper

MPDU

Append

Pad Bits (Zeros)

=

pad

N

Frame Control 2 Octets Access Information 2 Octets DestAddr 2 Octets SrcAddr 2 Octets Sequence Control 2 Octets

Transmitter Reference Block Diagram

R0… R4 0: 4 L0… L15 10: 25 RATE (5 bits) (sub) Frame LENGTH (16 bits) Number of Sub-Frames (5 bits) S0: S4 5: 9 (sub) Frame Number (5 bits) F0: F31 26: 30 CP mode (2 bits) C0: C1 32: 33 Reserved (5 bits) R0: R1 38: 39 PCESL mode (2 bits) U0: U1 34: 35 PCESP mode (2 bits) P0: P1 36: 37 FFT mode (1 bit) D0 31

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SLIDE 17

July 9, 2006

Ismail Lakkis, Tensorcom Slide 17

doc.: IEEE 802.15-0760-01-003c

Submission

Spreading Codes: Desired Features

! Quasi-perfect code: Low SLL (Side Lobe Level) and wide ZCZ (Zero Correlation Zone) for improved Detection ! Perfect code for channel estimation, i.e. zero SLL ! Binary codes (1 bit DAC versus multi-bit DAC) ! Zero-mean codes for improved DC offset cancellation ! Selected code should support a parallel Low complexity matched filter architecture ! Maximum code length of 128 for multiple XTALs support (up to 50 ppm, ±25 ppm @ Tx/ Rx). ! Should support SC & OFDM

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SLIDE 18

July 9, 2006

Ismail Lakkis, Tensorcom Slide 18

doc.: IEEE 802.15-0760-01-003c

Submission

Spreading Codes

! Golay complementary codes of various length N (aN ,bN) are the spreading codes of choice ! Each code has a low SLL and a wide ZCZ ! The combination of their periodic & aperiodic autocorrelation provides a perfect code ! Only 1 bit DAC & 1 bit ADC ! Admit a very low-complexity highly parallelizable architecture ! Key enabler for a low complexity synchronization, channel estimation & above all a comm on mode engine

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SLIDE 19

July 9, 2006

Ismail Lakkis, Tensorcom Slide 19

doc.: IEEE 802.15-0760-01-003c

Submission

! SYNC/ SFD codes:

  • a128 = [ 05C99C5005369CAFFA3663AF05369CAF]
  • b128 = [ F5396CA0F5C66C5F0AC6935FF5C66C5F]

! CES codes:

  • a256 = [ TBD]
  • b256 = [ TBD] ;

! Header & Data codes:

  • a64 = [ DE21212174748B74] ;
  • b64 = [ 2ED1D1D184847B84] ;

! Note : Hexadecimal convention: 5 = “0101” (i.e. MSB to LSB)

Spreading Codes summary

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SLIDE 20

July 9, 2006

Ismail Lakkis, Tensorcom Slide 20

doc.: IEEE 802.15-0760-01-003c

Submission

Preamble Golay codes

! D = [ 64 32 8 2 16 1 4] ; ! W = [ + + + + -+ + ] ! a128 = [ 05C99C5005369 ! CAFFA3663AF05369CAF] ! b128 = [ F5396CA0F5C6 ! 6C5F0AC6935FF5C66C5F]

Header/Data Golay codes

! D = [ 16 8 32 16 1 4] ; ! W = [ + -+ -+ + ] ! a64 = [ DE21212174748B74] ; ! b64 = [ 2ED1D1D184847B84] ;

  • 60
  • 40
  • 20

20 40 60 20 40 60 80 100 120 t/Tc Correlation Value Matched Filter Ouput to a or b

  • 100
  • 50

50 100 50 100 150 200 250 t/Tc Correlation Value Matched Filter to a + Matched filter to b 20 40 60 20 40 60 t/Tc Correlation Value M atc hed Filter O uput with data + 1 + 1 20 40 60 20 40 60 t/Tc Correlation Value M atc hed Filter O uput with data + 1 -1 20 40 60 20 40 60 t/Tc Correlation Value M atc hed Filter O uput with data + 1 + j 20 40 60 20 40 60 t/Tc Correlation Value M atc hed Filter O uput with data + 1 -j

Spreading Codes Properties

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SLIDE 21

July 9, 2006

Ismail Lakkis, Tensorcom Slide 21

doc.: IEEE 802.15-0760-01-003c

Submission

Spreading Codes Implementation

! Each Delay vector D and weight vector W specify a pair of complementary Golay codes ! Highly efficient Golay matched filter with only 14 adders for a length 128 code (“Budisin”) ! It provides simultaneous matched filtering with the two complementary codes at once. ! Enables same preamble for SC, OFDM & interoperability common mode

DD(0) DD(1) DD(M-1) + + + + + + + + +

  • W

1

W

1 − M

W input

n

x

n n

a x

n n

b x

⊗ function [a,b] = golaySub(M,N,D,W); a = [1 zeros(1,N-1)];b = a; for m=1:M, ii = mod([0:N-1]-D(m),N); an = W(m)*a + b(ii+(1)); bn = W(m)*a - b(ii+(1)); a = an;b = bn; end; return; Matlab Code

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SLIDE 22

July 9, 2006

Ismail Lakkis, Tensorcom Slide 22

doc.: IEEE 802.15-0760-01-003c

Submission

! Mapping:

  • Each set of 2 bits will select which Golay code is to be transmitted
  • One symbol = 64 chips
  • One symbol carries 2 bits of information
  • Effective spreading factor " 32
  • Modulation used for both header and data

! Differential Encoder:

  • Chip level differential encoder:

! Rotator:

  • Chip level π/ 2-rotation:

S2P 1 to 2

… , d2k, d2k+ 1, … d2k d2k+ 1 LUT d2kd2k+ 1 0 0 " + a64 0 1 " -a64 1 0 " + b64 1 1 " -b64 Chip Level DBPSK Chip Level π/ 2 Rotation an bn cn

1 1

= ⊕ =

− − n n n n

b a b b with

n n n

b j c =

Golay Symbol Mapper π/2-DBPSK Modulator Or GMSK Modulator*

The Modulator & Mapper

*I. Lakkis, J. Su, & S. Kato, “A Simple Coherent GMSK Demodulator”, PIMRC 2001

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SLIDE 23

July 9, 2006

Ismail Lakkis, Tensorcom Slide 23

doc.: IEEE 802.15-0760-01-003c

Submission

r0 r1 r2 r3 r14 r15

g1 g2 g3 g15 g0 Message block Input: m0, m1, m2, … , m238

First to enter encoder Last to enter encoder

Code Word Output: m238, … , m2 , m1 , m0, r15, …, r0

First out from encoder Last out from encoder

X Y X Y X Y

matlab code data = round(rand(8,239)) data = (2.^[0:7])*data parity = rsenc(gf(data,8),255,239); parity = parity(:,end-15:end); parity = reshape(de2bi(parity,8)',1,128); code = [data parity];

! Encoding Operation

  • Step 1. Reset Shift Register (SR) to all zeros.
  • Step 2. The 3 switches are placed in position X and the K = 239 message symbols are fed into the encoder in order of

decreasing index; the K message symbols are simultaneously sent out.

  • Step 3. After the last message symbol (m0) has been fed into the Shift Register (SR), the switches are moved to position Y.

At this point the SR contain the remainder generated by the division operation. These symbols are then shifted out of the SR.

! Systematic Encoding for an RS(K+16,K) shortened from RS(255,239) over GF(28)

  • Primitive polynomial:

P(z) = z8 + z4 + z3 + z2 + 1 with root z = 00000010

  • Generator polynomial:

g(x) = ∏i=1:16(x-zi)

  • Symbol representation:

m = b7z7 + b6z6 + … + b0 = [b7b6…b0] where b7 is the msb and b0 is the lsb

  • message polynomial:

m(x) = m0 + m1 x + ... + m238x238 with (mK:238 = 0)

  • Step 1. Multiply the message polynomial m(x) by x16, m(x)x16 = [0 0 ... 0 m0 m1 ... m238]
  • Step 2. Divide x6m(x) by g(x). Let r(x) be the remainder: x16m(x) = q(x) .g(x) + r(x)
  • Step 3. Set c(x) = x16m(x) + r(x) , i.e. c(x) = [m238 ...mK mK-1 … m0 r15... r0], mK-1 is transmitted first & r0 is transmitted

last in time

The Reed Solomon FEC over GF(28)

slide-24
SLIDE 24

July 9, 2006

Ismail Lakkis, Tensorcom Slide 24

doc.: IEEE 802.15-0760-01-003c

Submission

xn-1 xn xn-14 xn-15 sn vn

Serial Data In Scrambled/Descrambled Serial Data Out

D D D D

0011 1111 1111 111 Seed Value: xinit = [x-1 x-2 … x-15] 0000 0000 0000 1000 PRBS out first 16 bits: [x0 x1 … x15]

matlab code function [dataOut] = tcScrambler(dataIn,Fast)

shiftRegister = [0 0 ones(1,13)]; for k = 0:length(dataIn) -1, feedback = xor( shiftRegister(13+(1)) , shiftRegister(14+(1)) ); dataOut(k+(1)) = mod(dataIn(k+(1))+feedback , 2); shiftRegister = [feedback shiftRegister([0:13]+(1))]; end;

return;

The Scrambler

slide-25
SLIDE 25

July 9, 2006

Ismail Lakkis, Tensorcom Slide 25

doc.: IEEE 802.15-0760-01-003c

Submission

! Encoding Operation

  • Step 1. Reset Shift Register (SR) to all ones.
  • Step 2. The 3 switches are placed in position X and the K bits are fed into the encoder.
  • Step 3. After the last bit (m0) has been fed into the Shift Register (SR), the switches are moved to position Y. At this point

the SR contains the CRC bits. These bits are then shifted out of the SR and complemented.

! FCS: MAC Frame Payload (M = 32)

  • FCS generator polynomial:

g(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 = [ 111011011011100010000011001000001]

  • MAC payload message polynomial:

m(x) = m0 + m1 x + ... + mK-1xK-1 with (mK-1 = lsb of first octet of MAC payload)

! HCS: PHY & MAC headers (M = 16)

  • FCS generator polynomial:

g(x) = x16 + x12 + x5 + 1 = [ 10000100000010001]

  • PHY & MAC headers polynomial (m119 is first bit of PHY header & m0 is last bit of MAC header)

m(x) = m0 + ... + m79 x79 + m80 x80 + … + m119x119

The FCS & HCS

r0 r1 rM-2 rM-1

g1 g2 gM-2 gM-1 g0

Message block Input: m0, m1, …, mK-1 First to enter encoder Last out from encoder

X Y X Y X Y

matlab code (indexing from 1 rather than 0) r = ones(1,M); for k = 1:K, f = mod(d(k) + r(M),2); r = mod([0 r(1:M-1)] + f*g(1:M),2) end; r = xor(r(M:-1:1),1)

slide-26
SLIDE 26

July 9, 2006

Ismail Lakkis, Tensorcom Slide 26

doc.: IEEE 802.15-0760-01-003c

Submission

The Pulse Shaper

! The Pulse shaper is left up to the implementer. It can be im plemented in digital and/ or

  • analog. Exam ples:
  • 1. GMSK or Linearized GMSK pulse with BT= 0.5 (recommended);
  • 2. pure GMSK with BT = 0.5 (recommended);
  • 2. Square-root raised cosine with roll-off= 0.25 with clipping / lifting;
  • 3. Square-root raised cosine with roll-off= 0.25 without clipping
slide-27
SLIDE 27

July 9, 2006

Ismail Lakkis, Tensorcom Slide 27

doc.: IEEE 802.15-0760-01-003c

Submission

Unified Frame Format

! Unified Frame Format ! Key Features ! Frame Format: Single Carrier ! Frame Format: OFDM ! Frame Format: Common Mode

slide-28
SLIDE 28

July 9, 2006

Ismail Lakkis, Tensorcom Slide 28

doc.: IEEE 802.15-0760-01-003c

Submission

Long : Tpreamble = 2.963 µs Short: Tpreamble = 1.333 µs

PLCP Preamble PLCP Header PSDU Packet/Frame Sync Sequence (Long Preamble: 30 Codes, Short Preamble: 8 Codes) SFD: Start

Frame Delimiter

CES Channel Estimation Sequence

a128 a128 a128

  • a128

a256 a128

  • a128

aCP

128

aCP

128

b256 bCP bCP

aN & bN are a complementary Golay codes pair of length N

Data Slot PCES PCES Data Slot PCES Data Slot SC Data Burst aM 256 chips ~ 148ns (optional 512) SC Data Burst aM SC Data Burst aM aM 0, 64, 128, or 256 OFDM Data Symbol CP OFDM Data Symbol CP OFDM Data Symbol 512 chips ~ 300µs OFDM mode CP SC mode 32, 64, 96, & 128 0, 16, 32, & 64 (optional 32,64,96, 128) ±a64 ±b64 Common mode 64

Unified Frame Format Concept

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SLIDE 29

July 9, 2006

Ismail Lakkis, Tensorcom Slide 29

doc.: IEEE 802.15-0760-01-003c

Submission

! A PCES (Pilot CES) field is transmitted periodically to reacquire the channel in both SC and OFDM; ! Variable length Golay codes are used for this field; ! Preamble HW is reused during re-acquisition " no extra cost ! Mode specific frequency/ timing tracking

  • Pilot tones for OFDM
  • CP as a known Golay code for SC

! Highly complex channel tracking is no longer needed ! The OFDM FFT(512) engine can be implemented as 2 smaller FFT(256) engines allowing HW reuse in SC mode with FDE (Frequency domain Equalization) which requires FFT(256) & IFFT(256)

Unified Frame Format Features

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SLIDE 30

July 9, 2006

Ismail Lakkis, Tensorcom Slide 30

doc.: IEEE 802.15-0760-01-003c

Submission

! The modulation of choice for low complexity low power devices ! Support for 3 device classes:

  • Class I (LDR): Low-Data-Rate, Low-power, low-complexity (Constant Envelope option)

π/ 2-DBPSK/ GMSK with data rates 50Mbps-1.5Gbps

  • Class II (MDR): Medium-Data-Rate, Quasi-constant envelope (QPSK) with data rates up to 3Gbps
  • Class II I (HDR): High-Data-Rate, non-constant envelope (8PSK & 16QAM) with data rates up to

6Gbps

! Medium size FFT(256) & iFFT(256) for FDE is enough for all practical environments (optional 512 mode) ! Known Golay code of variable length will serve as CP. This puts the CP at works instead of being a Waste. ! The Golay prefix will be used for timing, frequency and channel tracking if desired. ! Pilot CES are used to re-acquire the channel

Frame Format: Single Carrier

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SLIDE 31

July 9, 2006

Ismail Lakkis, Tensorcom Slide 31

doc.: IEEE 802.15-0760-01-003c

Submission

Frame Format: OFDM

! The m odulation of choice for HDR (16-QAM and above), ! Data rates up to 6Gbps ! Allows future data rates extension without RF HW change ! FFT size of 512 allows operation in extremely harsh environments with very large delay spread ! Periodic pilot CES would alleviate the channel tracking task and reduces the sync engine trem endously ! SC with 16-QAM presents no advantages over OFDM ! We need both SC & OFDM for different applications!

slide-32
SLIDE 32

July 9, 2006

Ismail Lakkis, Tensorcom Slide 32

doc.: IEEE 802.15-0760-01-003c

Submission

Frame Format: Common Mode

! Common mode: necessary for interoperability between different devices & different networks ! It requires no additional circuitry to that used during preamble detection; it comes for free! ! Very low complexity with a single multiply and add (in serial implementation) ! Requires only Reed Solomon Code, already needed for the header!

! Used for beaconing, signaling and for BR (Base Rate) data packets

! The key enabler of collision avoidance between different networks

slide-33
SLIDE 33

July 9, 2006

Ismail Lakkis, Tensorcom Slide 33

doc.: IEEE 802.15-0760-01-003c

Submission

Unified PLCP Header

RES 6426 10000 RES 4820 01101 RES 5184 01110 RES 6048 01111 2232 3213 01010 3720 3888 01011 4463 4536 01100 RES 3213 10001: 11111 1860 3024 01001 930 2592 01000 5040 1728 00111 4320 1512 00110 2880 1296 00101 2520 864 00100 2160 432 00011 1440 216 00010 720 108 00001 50Mbps CM 00000

OFDM (Mbps) SC (Mbps) RATE Cyclic Prefix Length

128 64 11 96 32 10 64 16 01 32 00 00

OFDM/ Sc-512 SC-256 CP Mode PCES Length

RES 256 11 256 128 10 128 64 01 64 16 00

OFDM/ SC-512 SC-256 PCESL Mode

! If the number of sub-Frames = 1 than it is a default header,

  • therwise it is an aggregation header

! Header is nom inally transm itted at the default base rate of 50Mbps ! Optional Higher Header Rate for MDR & HDR

PCES Period

4096 4096 01 2048 2048 00

OFDM/ SC-512 SC-256 PCESP Mode

1512-6426Mbps 50-1296Mbps SC Rate 2160-5040 Mbps 720 or 930 Mbps 432 Mbps

  • 1-1

720-1440Mbps 50 Mbps 50 Mbps

  • 1+ 1

OFDM Rate Header Rate Header Rate SFD

R0… R4 0: 4 L0… L15 10: 25 RATE (5 bits) (sub) Frame LENGTH (16 bits) Number of Sub-Frames (5 bits) S0: S4 5: 9 (sub) Frame Number (5 bits) F0: F31 26: 30 CP mode (2 bits) C0:C1 32: 33 Reserved (5 bits) R0: R1 38: 39 PCESL mode (2 bits) U0: U1 34: 35 sub-Frame 1 RATE (5 bits) 40: 44 sub-Frame 2 RATE (5 bits) 45: 49 sub-Frame N FEC mode (5 bits)

35+ 5N: 39+ 5N

Default Header Aggregation Header

PCESP mode (2 bits) P0: P1 36: 37 FFT mode (1 bit) D0 31

1

FFT Mode

512 256

SC-FFT

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SLIDE 34

July 9, 2006

Ismail Lakkis, Tensorcom Slide 34

doc.: IEEE 802.15-0760-01-003c

Submission

Single Carrier Mode

! Key Features ! Rate Related Parameters ! Timing & Frame Related Parameters ! Short Spreading Codes ! Structured LDPC FEC

slide-35
SLIDE 35

July 9, 2006

Ismail Lakkis, Tensorcom Slide 35

doc.: IEEE 802.15-0760-01-003c

Submission

SC Rate Dependent Parameters

Device Data Rate Chip Rate Modulation Time FEC FEC Coded Bits Info Bits Class Mbps MHz Scheme Spreading Rate Type Per Burst Per Burst R RC Length: L RFEC NCBPS NI BPS I 108 1728 π/ 2-BPSK 8 0.500 LDPC 256 128 I 216 1728 π/ 2-BPSK 4 0.500 LDPC 256 128 I 432 1728 π/ 2-BPSK 2 0.500 LDPC 256 128 I 864 1728 π/ 2-BPSK 1 0.500 LDPC 256 128 I 1296 1728 π/ 2-BPSK 1 0.750 LDPC 256 192 I 1512 1728 π/ 2-BPSK 1 0.875 LDPC 256 224 II 1728 1728 π/ 2-QPSK 1 0.500 LDPC 256 128 II 2592 1728 π/ 2-QPSK 1 0.750 LDPC 256 192 II 3024 1728 π/ 2-QPSK 1 0.875 LDPC 256 224 II 3213 1728 π/ 2-QPSK 1 0.933 LDPC 256 238 III 3888 1728 π/ 2-8PSK 1 0.750 LDPC 256 192 III 4536 1728 π/ 2-8PSK 1 0.875 LDPC 256 224 III 4819.5 1728 π/ 2-8PSK 1 0.933 LDPC 256 238 III 5184 1728 π/ 2-16QAM 1 0.750 LDPC 256 192 III 6048 1728 π/ 2-16QAM 1 0.875 LDPC 256 224 III 6426 1728 π/ 2-16QAM 1 0.933 LDPC 256 238

SC: PSDU Default Rate-Dependent Parameters

slide-36
SLIDE 36

July 9, 2006

Ismail Lakkis, Tensorcom Slide 36

doc.: IEEE 802.15-0760-01-003c

Submission

SC Timing & Frame Parameters

Parameter Unit Formula RC MHz TC ns = 1/ RC Nburst chips ND 256 240 224 192 chips NCP 16 32 64 chips Tburst ns = 1 / Df TD 148.15 138.89 129.63 111.11 TCP 0.00 9.26 18.52 37.04 ns = NCP×TC Fburst MHz = 1/ Tburst

SC: Timing-Related Parameters

value 6.75 Data burst duration Burst rate 1728 0.579 Golay prefix duration 256 Burst duration (CP + Data) Known Golay prefix length Description Number of data chips Burst Size Chip duration Chip rate 148.15

Parameter Unit Nsync Default mode: 30 Fast m ode: 8 a128 Tsync Default mode: 2.222 Fast m ode: 0.593 µs Nsfd a128 Tsfd µs Nces a256/ b256 Tces µs Npre Default mode: 40 Fast m ode: 18 128 chips symbols Tpre Default mode: 2.963 Fast m ode: 1.333 µs Nphdr a64/b64 or s4 Tphdr Default m ode: 0.741 Fast m ode: 0.093 µs Nmhdr a64/b64 or s4 Tmhdr Default m ode: 1.481 Fast m ode: 0.185 µs Nchdr a64/b64 or s4 Tchdr Default m ode: 1.481 Fast m ode: 0.185 µs Nhdr a64/b64 or s4 Thdr Default m ode: 3.704 Fast m ode: 0.463 µs Nframe Tframe Ncframe Tpacket Ncpacket

SC Mode: Frame-Related Parameters

Duration of the packet sync seq. Number of symbols in the frame sync seq. 2 Description Value Number of symbols in the packet sync seq. Number of chips in the fram e Number of symbols in the data field Duration of the data field Duration of the frame sync sequence Number of symbols in the PHY header Number of symbols in the frame header 0.148 = Nframe×NFFT Duration of the header HCS & RSP Number of symbols in the channel estimation seq. 4×ceil[(8× LENGTH + 32)/ (4× NIBPS)] Nframe× Tburst 4 Duration of frame header Number of symbols in the MAC header Duration of the MAC header 200 40 Duration of the PLCP preamble 80 Duration of the PHY header 0.593 Duration of the channel estimation seq. Number of chips in the packet Default (Ncframe + 11520) Fast (Ncframe + 3104) packet duration = Tframe + Tpre + Thdr Number of symbols in the PLCP preamble Number of symbols in the header HCS & RSP 80

slide-37
SLIDE 37

July 9, 2006

Ismail Lakkis, Tensorcom Slide 37

doc.: IEEE 802.15-0760-01-003c

Submission

SC Frame Format

Long : Tpreamble = 2.963 µs Short: Tpreamble = 1.333 µs

PLCP Preamble PLCP Header PSDU Packet/Frame Sync Sequence (Long Preamble: 30 Codes, Short Preamble: 8 Codes) SFD: Start

Frame Delimiter

CES Channel Estimation Sequence

a128 a128 a128

  • a128

a256 a128

  • a128

aCP

128

aCP

128

b256 bCP bCP

aN & bN are a complementary Golay codes pair of length N

Data Slot PCES PCES Data Slot PCES Data Slot SC Data Burst aM 256 chips ~ 148ns (optional 512) SC Data Burst aM SC Data Burst aM aM 0, 64, 128, or 256 SC mode 0, 16, 32, & 64 (optional 32, 64, 96 & 128)

slide-38
SLIDE 38

July 9, 2006

Ismail Lakkis, Tensorcom Slide 38

doc.: IEEE 802.15-0760-01-003c

Submission

SC PLCP Header

RES 6426 10000 RES 4820 01101 RES 5184 01110 RES 6048 01111 2232 3213 01010 3720 3888 01011 4463 4536 01100 RES 3213 10001: 11111 1860 3024 01001 930 2592 01000 5040 1728 00111 4320 1512 00110 2880 1296 00101 2520 864 00100 2160 432 00011 1440 216 00010 720 108 00001 50Mbps CM 00000

OFDM (Mbps) SC (Mbps) RATE

  • If the number of sub-Frames = 1 than it is a default header,
  • therwise it is an aggregation header
  • Header is nom inally transm itted at the default base rate of

50Mbps

  • Optional Higher Header Rate for MDR & HDR

1512-6426Mbps 50-1296Mbps SC Rate 2160-5040 Mbps 720 or 930 Mbps 432 Mbps

  • 1-1

720-1440Mbps 50 Mbps 50 Mbps

  • 1+ 1

OFDM Rate Header Rate Header Rate SFD

Cyclic Prefix Length

128 64 11 96 32 10 64 16 01 32 00 00

OFDM/ Sc-512 SC-256 CP Mode PCES Length

RES 256 11 256 128 10 128 64 01 64 16 00

OFDM/ SC-512 SC-256 PCESL Mode PCES Period

4096 4096 01 2048 2048 00

OFDM/ SC-512 SC-256 PCESP Mode

R0… R4 0: 4 L0… L15 10: 25 RATE (5 bits) (sub) Frame LENGTH (16 bits) Number of Sub-Frames (5 bits) S0: S4 5: 9 (sub) Frame Number (5 bits) F0: F31 26: 30 CP mode (2 bits) C0:C1 32: 33 Reserved (5 bits) R0: R1 38: 39 PCESL mode (2 bits) U0: U1 34: 35 sub-Frame 1 RATE (5 bits) 40: 44 sub-Frame 2 RATE (5 bits) 45: 49 sub-Frame N FEC mode (5 bits)

35+ 5N: 39+ 5N

Default Header Aggregation Header

PCESP mode (2 bits) P0: P1 36: 37 FFT mode (1 bit) D0 31

1

FFT Mode

512 256

SC-FFT

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SLIDE 39

July 9, 2006

Ismail Lakkis, Tensorcom Slide 39

doc.: IEEE 802.15-0760-01-003c

Submission

SC Transmitter Reference Diagram

Scrambled PSDU Scramble & Append Scrambled Pad Bits Npad bits Scrambled FCS 32b Scrambled Frame Payload LENGTH octets Constellation Mapper Frame Payload FCS Pad Bits (zeros)

( )

  (

)

32 8 / 32 8 + × − + × × = LENGTH N LENGTH N N

IBPS IBPS pad

LENGTH : Number of octets in the frame payload 32 : FCS length in bits NIBPS : Number of information bits per slot

LDPC Encoder Preamble, CP, PCES I nsertion Chip Pulse Shaper Analog & RF π/ 2 rotator Spreader

slide-40
SLIDE 40

July 9, 2006

Ismail Lakkis, Tensorcom Slide 40

doc.: IEEE 802.15-0760-01-003c

Submission

Short Spreading Codes

! For low spreading code length (8 and below), there are no good codes. ! Use a varying spreading code generated by an LFSR

  • SC time spreading and
  • OFDM frequency spreading

[ x-1 x-2 …x-15] = [ xx11 1111 1111 1111] Spreader seed ID = [ 0 0] or [ 0 1] or [ 1 0] or [ 1 1] xn-1 xn xn-14 xn-15

dn sn Serial Data In Spread Data Out D D D D @ rate R @ chip Rate

matlab code function [dataOut] = tcSpreader(dataIn,spreaderSeedId,Fast) shiftRegister = [spreaderSeedId ones(1,13)]; for k = 0:length(dataIn) -1, feedback = xor( shiftRegister(13+(1)) , shiftRegister(14+(1)) ); dataOut(k+(1)) = mod(dataIn(k+(1))+feedback , 2); shiftRegister = [feedback shiftRegister([0:13]+(1))]; end; return;

slide-41
SLIDE 41

July 9, 2006

Ismail Lakkis, Tensorcom Slide 41

doc.: IEEE 802.15-0760-01-003c

Submission

The Constellation Mapper

8PSK encoding table

010 000 111 dI(k) dQ(k) b3kb3k+ 1b3k+ 2 001 011 110 011 100 exp(jπ/ 4) 001 exp(j3π/ 4) 010 exp(jπ/ 2) 011 exp(j7π/ 4) 100 exp(j3π/ 2) 101 exp(jπ) 110 exp(j5π/ 4) exp(j0) IQ-out 111 000 Input Bit b3k b3k+1 b3k+2

QPSK encoding table

( ) ( ) [ ]

... , 2 , 1 , , 1 2 1 2 2 1

2 1 2

= − + − =

+

k b j b d

k k k

11 10 01 00 dI(k) dQ(k) + 1

  • 1

b2kb2k+ 1 + 1

  • 1

+ 1

  • 1

I-out 1 Input Bit b2k + 1

  • 1

Q-out 1 Input Bit b2k+1

( )

... , 2 , 1 , , 1 2 = − = k b d

k k

1 dI(k) + 1

  • 1

+ 1

  • 1

I-out 1 Input Bit bk

BPSK encoding table

slide-42
SLIDE 42

July 9, 2006

Ismail Lakkis, Tensorcom Slide 42

doc.: IEEE 802.15-0760-01-003c

Submission

The LPDC Encoder

! No interleaving is required ! Supports rates ½ , ¾ , and 7/ 8 ! Very low complexity systematic encoder ! Low complexity highly parallelizable decoder (gate count ~ 150Kgates) ! Throughput matched to that of RS ! 1 RS and 1 LDPC Decoder engine is needed for LDR devices ! Throughput of 1728 Mbps with Master clock of 216 MHz (BW/ 8) and 64 iterations 576 576 576 NN 6 10 14 dmin 504 432 288 KK 7/8 3/4 1/2 Rate

slide-43
SLIDE 43

July 9, 2006

Ismail Lakkis, Tensorcom Slide 43

doc.: IEEE 802.15-0760-01-003c

Submission

The LDPC: Rate ¾ & 7/8 Parity Check Matrices

! Parity check matrix H is specified by an exponent matrix E, i.e. H = JE ! Matrix J is the cyclic shift of the 18x18 I dentity matrix, i.e. ! J∞ = 0; J0 = I ; J18 = I

E78: Rate 7/8 E34: Rate 3/4                   =

×

1 1 1 1

18 18

K O O O K M M O O M O K K O M J

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 11 9 10 4 15 2 5 12 16 16 10 5 13 2 8 10 5 10 6 5 17 10 8 6 7 16 2 ∞ ∞ ∞ 2 10 2 11 9 5 4 15 2 10 12 16 16 8 5 13 2 6 10 5 10 8 5 17 10 6 7 16 7 2 ∞ ∞ 3 9 10 2 11 2 5 4 15 16 10 12 16 2 8 5 13 10 6 10 5 10 8 5 17 16 6 7 8 7 2 ∞ 4 11 9 10 2 15 2 5 4 16 16 10 12 13 2 8 5 5 10 6 10 17 10 8 5 7 16 6 5 8 7 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 ∞ 9 ∞ 4 ∞ ∞ 5 12 ∞ 16 ∞ 5 ∞ 2 ∞ 10 5 ∞ ∞ ∞ ∞ 10 8 ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ 11 ∞ 10 ∞ 15 2 ∞ ∞ 16 ∞ 10 ∞ 13 ∞ 8 ∞ ∞ 10 6 5 17 ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 ∞ 2 ∞ 9 5 4 ∞ ∞ ∞ 12 ∞ 16 ∞ 5 ∞ 2 ∞ 10 5 ∞ 8 ∞ ∞ 10 ∞ ∞ 7 16 ∞ 2 ∞ ∞ 4 10 ∞ 11 ∞ ∞ ∞ 15 2 10 ∞ 16 ∞ 8 ∞ 13 ∞ 6 ∞ ∞ 10 ∞ 5 17 ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ 5 9 ∞ 2 ∞ ∞ 5 4 ∞ 16 ∞ 12 ∞ 2 ∞ 5 ∞ ∞ ∞ 10 5 10 8 ∞ ∞ 16 ∞ ∞ 7 ∞ ∞ ∞ ∞ 6 ∞ 10 ∞ 11 2 ∞ ∞ 15 ∞ 10 ∞ 16 ∞ 8 ∞ 13 10 6 ∞ ∞ ∞ ∞ 5 17 ∞ 6 ∞ ∞ ∞ ∞ ∞ 7 ∞ 9 ∞ 2 ∞ ∞ 5 4 ∞ 16 ∞ 12 ∞ 2 ∞ 5 5 ∞ ∞ 10 ∞ 10 8 ∞ 7 16 ∞ ∞ 5 ∞ ∞ 2 8 11 ∞ 10 ∞ 15 2 ∞ ∞ 16 ∞ 10 ∞ 13 ∞ 8 ∞ ∞ 10 6 ∞ 17 ∞ ∞ 5 ∞ ∞ 6 ∞ 8 7 ∞

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SLIDE 44

July 9, 2006

Ismail Lakkis, Tensorcom Slide 44

doc.: IEEE 802.15-0760-01-003c

Submission

The LDPC: Rate ½ Parity Check Matrix

E12: Rate 1/2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 ∞ ∞ ∞ 4 ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 9 ∞ ∞ ∞ ∞ 5 5 ∞ ∞ ¥ 10 ∞ ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 ∞ 11 ∞ ∞ ∞ 15 ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ 6 ∞ 17 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 4 ∞ ∞ ∞ 10 ∞ ∞ 2 ∞ ∞ 13 ∞ ¥ ∞ ∞ 10 ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 5 ∞ 2 ∞ ∞ ∞ 4 ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ 7 ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ 6 ∞ ∞ ∞ 9 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ ∞ ∞ ∞ ∞ 16 ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 7 ∞ ∞ 11 ∞ ∞ ∞ 15 ∞ 8 ∞ ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ 17 ∞ ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ ∞ 8 10 ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 13 ∞ ∞ ∞ ∞ 10 ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ ∞ 9 ∞ ∞ 2 ∞ ∞ ∞ 4 ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 5 10 ∞ ∞ ∞ ∞ ∞ ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 10 9 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 11 ∞ ∞ ∞ 11 ∞ ∞ ∞ 15 ∞ 8 ∞ ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ 17 ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 12 ∞ 10 ∞ ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 13 10 ∞ ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 13 ∞ ∞ ∞ 2 ∞ ∞ ∞ 4 ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ 7 ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ 12 14 ∞ 9 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞ ∞ ∞ 2 ∞ 16 ∞ ∞ 15 11 ∞ ∞ ∞ 15 ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ 6 ∞ 17 ∞ ∞ ∞ ∞ ∞ ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ 10 ∞ 16 ∞ ∞ 10 ∞ ∞ 2 ∞ ∞ 13 ∞ ∞ ∞ ∞ 10 ∞ ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞

slide-45
SLIDE 45

July 9, 2006

Ismail Lakkis, Tensorcom Slide 45

doc.: IEEE 802.15-0760-01-003c

Submission

The LDPC: Performance

slide-46
SLIDE 46

July 9, 2006

Ismail Lakkis, Tensorcom Slide 46

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM Mode

! Rate Dependent Parameters ! Timing Related Parameters ! Frame Related Parameters ! Transmitter Reference Diagram ! FEC Option I ! FEC Option II ! Constellation Mapper ! OFDM Modulator ! PSD

slide-47
SLIDE 47

July 9, 2006

Ismail Lakkis, Tensorcom Slide 47

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM Rate Dependent Parameters

Data Rate Chip Rate Modulation Frequency FEC FEC Coded Bits Info Bits Mbps MHz Scheme Spreading Rate Type Per Symbol Per Symbol R RC Length: L RFEC NCBPS NIBPS 720 1728 QPSK 2 0.500 LDPC 480 240 1440 1728 QPSK 1 0.500 LDPC 480 240 2160 1728 QPSK 1 0.750 LDPC 480 360 2520 1728 QPSK 1 0.875 LDPC 480 420 2880 1728 16QAM 1 0.500 LDPC 480 240 4320 1728 16QAM 1 0.750 LDPC 480 360 5040 1728 16QAM 1 0.875 LDPC 480 420 930 1728 QPSK 1 0.333 Convolutional/ RS 480 160 1860 1728 QPSK 1 0.667 Convolutional/ RS 480 320 2232 1728 QPSK 1 0.800 Convolutional/ RS 480 384 3720 1728 16QAM 1 0.667 Convolutional/ RS 480 320 4463 1728 16QAM 1 0.800 Convolutional/ RS 480 384

OFDM: PSDU Default Rate-Dependent Parameters

slide-48
SLIDE 48

July 9, 2006

Ismail Lakkis, Tensorcom Slide 48

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM Timing Parameters

Parameter Unit Formula R C MHz T C ns = 1/R C N FFT subcarriers N D subcarriers N PF subcarriers N PR subcarriers N P subcarriers N G subcarriers N DC subcarriers N Z subcarriers N U N CP 32 64 96 128 Chips D f MHz = R C /N FFT B U MHz = N U ×D f T FFT ns = 1 /D f T CP 18.52 37.04 55.56 74.07 ns = N CP ×T C T SYM 314.81 333.33 351.85 370.37 ns = T FFT + T CP F SYM 3.176 3 2.842 2.7 MHz = 1/T SYM N CPSYM 544 576 608 640 Chips = N FFT + N CP

OFDM: Timing-Related Parameters

510 Number of used subcarriers Used bandwidth 1721.25 Symbol rate Number of chips per symbol 3.375 296.30 value Number of running pilot subcarriers Number of fixed pilot subcarriers 1728 0.579 Number of zero (non DC) subcarriers Symbol duration Cyclic prefix duration 512 IFFT/FFT duration Subcarrier frequency spacing Cyclic prefix length 486 8 Total number of pilot subcarriers Number of guard subcarriers Number of DC subcarriers 16 24 1 1 Description Number of data subcarriers FFT Size Chip duration Chip rate

slide-49
SLIDE 49

July 9, 2006

Ismail Lakkis, Tensorcom Slide 49

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM Frame Related Parameters

Parameter Unit N sync Default mode: 30 Fast mode: 8 a128 T sync Default mode: 2.222 Fast mode: 0.593 µs N sfd a128 T sfd µs N ces a256/ b256 T ces µs N pre Default mode: 40 Fast mode: 18 128 chips symbols T pre Default mode: 2.963 Fast mode: 1.333 µs N phdr a64/b64 or s4 T phdr Default mode: 0.741 Fast mode: 0.093 µs N mhdr a64/b64 or s4 T mhdr Default mode: 1.481 Fast mode: 0.185 µs N chdr a64/b64 or s4 T chdr Default mode: 1.481 Fast mode: 0.185 µs N hdr a64/b64 or s4 T hdr Default mode: 3.704 Fast mode: 0.463 µs N frame symbols T frame µs N cframe chips T packet µs N cpacket chips

OFDM Mode: Frame-Related Parameters

Number of symbols in the packet sync seq. Duration of the packet sync seq. Number of symbols in the frame sync seq. 2 Description Value Number of chips in the frame Number of symbols in the data field Duration of the data field Duration of the frame sync sequence 0.148 N frame ×(N CP +N FFT ) Duration of the header HCS & RSP Number of symbols in the channel estimation seq. 4 ×ceil[ (8×LENGTH + 32)/(4×NIBPS)] N frame ×T SYM 4 Duration of frame header Number of symbols in the MAC header Duration of the MAC header Number of symbols in the PHY header Number of symbols in the frame header 200 40 Duration of the PLCP preamble 80 Duration of the PHY header 0.593 Duration of the channel estimation seq. Number of chips in the packet Default: (N cframe + 11520 ) Fast: (N cframe + 3104 ) packet duration T frame + T pre + T hdr Number of symbols in the PLCP preamble Number of symbols in the header HCS & RSP 80

slide-50
SLIDE 50

July 9, 2006

Ismail Lakkis, Tensorcom Slide 50

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM Frame Format

PLCP Preamble PLCP Header PSDU Packet/Frame Sync Sequence (Long Preamble: 30 Codes, Short Preamble: 8 Codes) SFD Start Frame Delimiter CES Channel Estimation Sequence

a128 a128 a128

  • a128

a256 a128

  • a128

aCP Long : Tpreamble = 2.963 µs Short: Tpreamble = 1.333 µs 128 aCP 128 b256 bCP bCP aN & bN are a complementary Golay codes pair of length N OFDM Data Symbol CP OFDM Data Symbol CP OFDM Data Symbol 512 chips ~ 300µs CP 32, 64, 96, & 128 Data Slot PCES PCES Data Slot PCES Data Slot 0, 64, 128, or 256

slide-51
SLIDE 51

July 9, 2006

Ismail Lakkis, Tensorcom Slide 51

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM PLCP Header

RES 6426 10000 RES 4820 01101 RES 5184 01110 RES 6048 01111 2232 3213 01010 3720 3888 01011 4463 4536 01100 RES 3213 10001: 11111 1860 3024 01001 930 2592 01000 5040 1728 00111 4320 1512 00110 2880 1296 00101 2520 864 00100 2160 432 00011 1440 216 00010 720 108 00001 50Mbps CM 00000

OFDM (Mbps) SC (Mbps) RATE

! If the number of sub-Frames = 1 than it is a default header,

  • therwise it is an aggregation header

! Header is nom inally transm itted at the default base rate of 50Mbps ! Optional Higher Header Rate for MDR & HDR

1512-6426Mbps 50-1296Mbps SC Rate 2160-5040 Mbps 720 or 930 Mbps 432 Mbps

  • 1-1

720-1440Mbps 50 Mbps 50 Mbps

  • 1+ 1

OFDM Rate Header Rate Header Rate SFD

Cyclic Prefix Length

128 64 11 96 32 10 64 16 01 32 00 00

OFDM/ Sc-512 SC-256 CP Mode PCES Length

RES 256 11 256 128 10 128 64 01 64 16 00

OFDM/ SC-512 SC-256 PCESL Mode PCES Period

4096 4096 01 2048 2048 00

OFDM/ SC-512 SC-256 PCESP Mode

R0… R4 0: 4 L0… L15 10: 25 RATE (5 bits) (sub) Frame LENGTH (16 bits) Number of Sub-Frames (5 bits) S0: S4 5: 9 (sub) Frame Number (5 bits) F0: F31 26: 30 CP mode (2 bits) C0:C1 32: 33 Reserved (5 bits) R0: R1 38: 39 PCESL mode (2 bits) U0: U1 34: 35 sub-Frame 1 RATE (5 bits) 40: 44 sub-Frame 2 RATE (5 bits) 45: 49 sub-Frame N FEC mode (5 bits)

35+ 5N: 39+ 5N

Default Header Aggregation Header

PCESP mode (2 bits) P0: P1 36: 37 FFT mode (1 bit) D0 31

1

FFT Mode

512 256

SC-FFT

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SLIDE 52

July 9, 2006

Ismail Lakkis, Tensorcom Slide 52

doc.: IEEE 802.15-0760-01-003c

Submission

Transmitter Reference Diagram

Scrambled PSDU Scramble & Append Scrambled Pad Bits Npad bits Unscrambled Tail Bits T bits Scrambled FCS 32b Scrambled Frame Payload LENGTH octets QPSK/ QAM Mapper T Zero Bits Frame Payload FCS T Zero Bits (Tail Bits) Pad Bits (zeros)

( )

  (

)

T LENGTH N T LENGTH N N

S IBP S IBP pad

+ + × − + + × × = 32 8 / 32 8

4 4

LENGTH : Number of octets in the frame payload 32 : FCS length in bits T : Number of tail bits (0 for LDPC & 192 for convolutional) NIBP4S : Number of information bits per four OFDM symbols

FEC Coder, Puncturer & I nterleaver Preamble, Pilot/ DC I nsertion I FFT CP I nsertion Symbol Shaper Analog & RF LPF

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SLIDE 53

July 9, 2006

Ismail Lakkis, Tensorcom Slide 53

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option I: Structure

! Outer Reed Solomon RS(255,247) of rate 0.968:

  • For a master clock of 216MHz, one RS encoder has a throughput of

1728 Mbps

  • Up to implementer how to achieve higher throughput necessary with

16QAM (Master clock / buffering & multiple instantiation of RS encoder)

! Thirty two parallel convolutional encoders:

! To achieve 16QAM throughput with a master clock of 216MHz ! To enable future extension to 64QAM with a master clock of 432MHz

Convolutional Encoder & Puncturer Reed Solomon Encoder Demux 1: 32 Convolutional Encoder & Puncturer Convolutional Encoder & Puncturer Mux 32: 1 I nterleaver

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SLIDE 54

July 9, 2006

Ismail Lakkis, Tensorcom Slide 54

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option I: The Convolutional Encoder

An xn

D D D D D D

Bn Cn

Convolutional encoder: R = 1/3, K = 7

Convolutional Encoder & Puncturer

7 12 4/ 7 7 12 4/ 5 5 9 3/ 4 6 9 2/ 3 1 3 1/ 2 #Stolen Bits Period Bit Stolen Data Encoded date Source Data Rate

x0 A0 B0 C0 A0 C0 x0 x1 x2 A0 B0 C0 A1 B1 C1 A2 B2 C2 A0 C1 B0 C2 x0 x1 x0 x1 x2 x3 A0 B0 C0 A1 B1 C1 A2 B2 C2 A3 B3 C3 A0 B1 A1 A2 C2 A0 B0 C0 A1 B1 C1 A2 B2 C2 A3 B3 C3 A0 B1 A1 A2 C2 B3 x0 x1 x2 x3 A0 B0 C0 A1 B1 C1 A2 B2 C2 A3 B3 C3 A0 A2 B1 C2 A3 A3 C3

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SLIDE 55

July 9, 2006

Ismail Lakkis, Tensorcom Slide 55

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option I: The Interleaver

! Symbol I nterleaver: permutes bits across 4 consecutive OFDM symbols " frequency & time diversity ! I ntra-symbol tone interleaver: permutes the bits within an OFDM symbol across the data subcarriers " frequency diversity and robustness against narrow-band interferers

1944 Block Size Bit Interleaver 486 Block Size NCOL NROW NCOL NROW 486 4 54 1944 Coded Bits/ 4 OFDM Symbols (NCBP4S) 9 486 Tone Interleaver Coded Bits/ OFDM Symbol (NCBPS) Bit I nterleaver Block of NCBP4S Bits a[i] , i = 0: NCBP4S -1 aB[i] , i = 0: NCBP4S -1 Tone I nterleaver aT[i] , i = 0: NCBP4S -1 1 2 3 4 5 6 7

1940 1941 1942 1943

Write I n Read Out 4 486 Write I n Read Out 9

Interleave NCBPS bits @ a time aB([ 0: NCBPS 1] + r×NCBPS), r= 0: 3

1 … 8 9 10 … 17

477 478 … 485

One Block of NCBPS bits @ a time aT([ 0: NCBPS 1] + r×NCBPS), r= 0: 3

54

slide-56
SLIDE 56

July 9, 2006

Ismail Lakkis, Tensorcom Slide 56

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option II: LPDC

! No interleaving is required ! Supports rates ½ , ¾ , and 7/ 8 ! Very low complexity systematic encoder ! Low complexity highly parallelizable decoder (gate count ~ 150Kgates) ! Throughput matched to that of RS ! 1 RS and 1 LDPC Decoder engine is needed for LDR devices ! Throughput of 1728 Mbps with Master clock of 216 MHz (BW/ 8) and 64 iterations 576 576 576 NN 6 10 14 dmin 504 432 288 KK 7/8 3/4 1/2 Rate

slide-57
SLIDE 57

July 9, 2006

Ismail Lakkis, Tensorcom Slide 57

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option II: Rate ¾ & 7/8 Parity Check Matrices

! Parity check matrix H is specified by an exponent matrix E, i.e. H = JE ! Matrix J is the cyclic shift of the 18x18 I dentity matrix, i.e. ! J∞ = 0; J0 = I ; J18 = I

E78: Rate 7/8 E34: Rate 3/4                   =

×

1 1 1 1

18 18

K O O O K M M O O M O K K O M J

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 11 9 10 4 15 2 5 12 16 16 10 5 13 2 8 10 5 10 6 5 17 10 8 6 7 16 2 ∞ ∞ ∞ 2 10 2 11 9 5 4 15 2 10 12 16 16 8 5 13 2 6 10 5 10 8 5 17 10 6 7 16 7 2 ∞ ∞ 3 9 10 2 11 2 5 4 15 16 10 12 16 2 8 5 13 10 6 10 5 10 8 5 17 16 6 7 8 7 2 ∞ 4 11 9 10 2 15 2 5 4 16 16 10 12 13 2 8 5 5 10 6 10 17 10 8 5 7 16 6 5 8 7 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 ∞ 9 ∞ 4 ∞ ∞ 5 12 ∞ 16 ∞ 5 ∞ 2 ∞ 10 5 ∞ ∞ ∞ ∞ 10 8 ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ 11 ∞ 10 ∞ 15 2 ∞ ∞ 16 ∞ 10 ∞ 13 ∞ 8 ∞ ∞ 10 6 5 17 ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 ∞ 2 ∞ 9 5 4 ∞ ∞ ∞ 12 ∞ 16 ∞ 5 ∞ 2 ∞ 10 5 ∞ 8 ∞ ∞ 10 ∞ ∞ 7 16 ∞ 2 ∞ ∞ 4 10 ∞ 11 ∞ ∞ ∞ 15 2 10 ∞ 16 ∞ 8 ∞ 13 ∞ 6 ∞ ∞ 10 ∞ 5 17 ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ 5 9 ∞ 2 ∞ ∞ 5 4 ∞ 16 ∞ 12 ∞ 2 ∞ 5 ∞ ∞ ∞ 10 5 10 8 ∞ ∞ 16 ∞ ∞ 7 ∞ ∞ ∞ ∞ 6 ∞ 10 ∞ 11 2 ∞ ∞ 15 ∞ 10 ∞ 16 ∞ 8 ∞ 13 10 6 ∞ ∞ ∞ ∞ 5 17 ∞ 6 ∞ ∞ ∞ ∞ ∞ 7 ∞ 9 ∞ 2 ∞ ∞ 5 4 ∞ 16 ∞ 12 ∞ 2 ∞ 5 5 ∞ ∞ 10 ∞ 10 8 ∞ 7 16 ∞ ∞ 5 ∞ ∞ 2 8 11 ∞ 10 ∞ 15 2 ∞ ∞ 16 ∞ 10 ∞ 13 ∞ 8 ∞ ∞ 10 6 ∞ 17 ∞ ∞ 5 ∞ ∞ 6 ∞ 8 7 ∞

slide-58
SLIDE 58

July 9, 2006

Ismail Lakkis, Tensorcom Slide 58

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option II: Rate ½ Parity Check Matrix

E12: Rate 1/2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 ∞ ∞ ∞ 4 ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 9 ∞ ∞ ∞ ∞ 5 5 ∞ ∞ ¥ 10 ∞ ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 ∞ 11 ∞ ∞ ∞ 15 ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ 6 ∞ 17 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 4 ∞ ∞ ∞ 10 ∞ ∞ 2 ∞ ∞ 13 ∞ ¥ ∞ ∞ 10 ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 5 ∞ 2 ∞ ∞ ∞ 4 ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ 7 ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ 6 ∞ ∞ ∞ 9 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ ∞ ∞ ∞ ∞ 16 ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 7 ∞ ∞ 11 ∞ ∞ ∞ 15 ∞ 8 ∞ ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ 17 ∞ ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ ∞ 8 10 ∞ ∞ ∞ ∞ ∞ ∞ 2 ∞ ∞ 13 ∞ ∞ ∞ ∞ 10 ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ ∞ 9 ∞ ∞ 2 ∞ ∞ ∞ 4 ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 5 10 ∞ ∞ ∞ ∞ ∞ ∞ 7 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 10 9 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 11 ∞ ∞ ∞ 11 ∞ ∞ ∞ 15 ∞ 8 ∞ ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ 17 ∞ ∞ 6 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 12 ∞ 10 ∞ ∞ 2 ∞ ∞ ∞ ∞ ∞ ∞ 13 10 ∞ ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 13 ∞ ∞ ∞ 2 ∞ ∞ ∞ 4 ∞ 2 ∞ ∞ 5 ∞ ∞ ∞ ∞ 10 ∞ ∞ 7 ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ ∞ ∞ 12 14 ∞ 9 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ 10 ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞ ∞ ∞ 2 ∞ 16 ∞ ∞ 15 11 ∞ ∞ ∞ 15 ∞ ∞ ∞ ∞ ∞ 8 ∞ ∞ ∞ 6 ∞ 17 ∞ ∞ ∞ ∞ ∞ ∞ 6 ∞ ∞ 7 ∞ ∞ ∞ 10 ∞ 16 ∞ ∞ 10 ∞ ∞ 2 ∞ ∞ 13 ∞ ∞ ∞ ∞ 10 ∞ ∞ ∞ ∞ ∞ 5 ∞ ∞ ∞ ∞ 8 ∞ ∞ 16 ∞ ∞ ∞

slide-59
SLIDE 59

July 9, 2006

Ismail Lakkis, Tensorcom Slide 59

doc.: IEEE 802.15-0760-01-003c

Submission

FEC Option II: Performance

slide-60
SLIDE 60

July 9, 2006

Ismail Lakkis, Tensorcom Slide 60

doc.: IEEE 802.15-0760-01-003c

Submission

The Constellation Mapper

16-QAM mapping QPSK encoding table

1010 1110 0110 0010 1011 1111 0111 0011 1001 1101 0101 0001 1000 1100 0100 0000 dI(k) dQ(k) + 1 + 3

  • 1
  • 3

( ) ( ) [ ]

... , 2 , 1 , , 1 2 1 2 2 1

2 1 2

= − + − =

+

k b j b d

k k k

11 10 01 00 dI(k) dQ(k) + 1

  • 1

b2kb2k+ 1 + 1

  • 1

( )( ) ( )( ) [ ]

... , 2 , 1 , , 2 3 1 2 2 3 1 2 10 1

3 4 2 4 1 4 4

= − − + − − =

+ + +

k b b j b b d

k k k k k

b4kb4k+ 1b4k+ 2b4k+ 3 + 1

  • 1

I-out 1 Input Bit b2k + 1

  • 1

Q-out 1 Input Bit b2k+1

  • 1

01 + 1 11 + 3

  • 3

I-out 10 00 Input Bit b4k b4k+1

  • 1

01 + 1 11 + 3

  • 3

I-out 10 00 Input Bit b4k b4k+1

slide-61
SLIDE 61

July 9, 2006

Ismail Lakkis, Tensorcom Slide 61

doc.: IEEE 802.15-0760-01-003c

Submission

The OFDM Modulator

IFFT Y0 =0 Y1 Y63 Y64 Y127 Y128 Y255 Y-256 = 0 Y-255 Y-193 Y-192 Y-129 Y-128 Y-63 Y-64 Y-1 Y191 Y192 s0 s1 s63 s64 s127 s128 s255 s256 s257 s319 s320 s383 s384 s447 s448 s511 s191 s192

  • 230: 32: 250
  • 224: 60: 224

8n+ 6

  • 226: 32: 254
  • 224: 60: 224

8n+ 7

  • 234: 32: 246
  • 224: 60: 224

8n+ 5

  • 238: 32: 242
  • 224: 60: 224

8n+ 4

  • 242: 32: 238
  • 224: 60: 224

8n+ 3

  • 246: 32: 234
  • 224: 60: 224

8n+ 2

  • 250: 32: 230
  • 224: 60: 224

8n+ 1

  • 254: 32: 226
  • 224: 60: 224

8n Variable Pilots (16) Fixed Pilots (8)

Symbol

# Pilots for CP ≥ 96

  • 228: 32: 252
  • 224: 60: 224

4n+ 3

  • 236: 32: 244
  • 224: 60: 224

4n+ 2

  • 244: 32: 236
  • 224: 60: 224

4n+ 1

  • 252: 32: 228
  • 224: 60: 224

4n Variable Pilots (16) Fixed Pilots (8)

Symbol

# Pilots for CP ≤ 64 Guard Subcarriers 2 Zero & DC Subcarriers 24 Pilot Subcarriers 486 Data Subcarriers ( ) ( )

511 : 1

2 / 2 / 2

= =

− =

k e Y N s

u u FFT

N N m N mk j n m FFT n k π

S0 S1 … S510 S511 S512-CP … S511

! CP Default value is 64, Optional: 32, 96, & 128

slide-62
SLIDE 62

July 9, 2006

Ismail Lakkis, Tensorcom Slide 62

doc.: IEEE 802.15-0760-01-003c

Submission

Pilot Structure (CP ≤ 64)

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4n 4n+1 0 4n+2 0 4n+3 0

  • 192
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4n 4n+1 4n+2 4n+3

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4n 4n+1 4n+2 4n+3

  • 64
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  • 2
  • 1

4n 4n+1 4n+2 4n+3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 4n 4n+1 0 4n+2 0 4n+3 0 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 4n 4n+1 4n+2 4n+3 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 4n 4n+1 4n+2 4n+3 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 4n 4n+1 4n+2 4n+3

slide-63
SLIDE 63

July 9, 2006

Ismail Lakkis, Tensorcom Slide 63

doc.: IEEE 802.15-0760-01-003c

Submission

Pilot Structure (CP = 128)

  • 256
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8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7

  • 192
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8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7

  • 128
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  • 109
  • 108
  • 107
  • 106
  • 105
  • 104
  • 103
  • 102
  • 101
  • 100
  • 99
  • 98
  • 97
  • 96
  • 95
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  • 93
  • 92
  • 91
  • 90
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  • 86
  • 85
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  • 81
  • 80
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  • 77
  • 76
  • 75
  • 74
  • 73
  • 72
  • 71
  • 70
  • 69
  • 68
  • 67
  • 66
  • 65

8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7

  • 64
  • 63
  • 62
  • 61
  • 60
  • 59
  • 58
  • 57
  • 56
  • 55
  • 54
  • 53
  • 52
  • 51
  • 50
  • 49
  • 48
  • 47
  • 46
  • 45
  • 44
  • 43
  • 42
  • 41
  • 40
  • 39
  • 38
  • 37
  • 36
  • 35
  • 34
  • 33
  • 32
  • 31
  • 30
  • 29
  • 28
  • 27
  • 26
  • 25
  • 24
  • 23
  • 22
  • 21
  • 20
  • 19
  • 18
  • 17
  • 16
  • 15
  • 14
  • 13
  • 12
  • 11
  • 10
  • 9
  • 8
  • 7
  • 6
  • 5
  • 4
  • 3
  • 2
  • 1

8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 8n 8n+1 8n+2 8n+3 8n+4 8n+5 8n+6 8n+7

slide-64
SLIDE 64

July 9, 2006

Ismail Lakkis, Tensorcom Slide 64

doc.: IEEE 802.15-0760-01-003c

Submission

OFDM PSD

! Symbol Shaper & LPF are left to the implementer

slide-65
SLIDE 65

July 9, 2006

Ismail Lakkis, Tensorcom Slide 65

doc.: IEEE 802.15-0760-01-003c

Submission

MAC Enhancements

slide-66
SLIDE 66

July 9, 2006

Ismail Lakkis, Tensorcom Slide 66

doc.: IEEE 802.15-0760-01-003c

Submission

Aggregation Mode

  • PHY aggregation mode is highly efficient, minimizes the memory requirem ent at the

device and is compliant with IEEE802.15.3b MAC

  • MAC should support very lengthy MSDUs (and consequently very long MPDUs) or

aggregated MPDUs,;

  • PHY will fragment the frame into subframes, protect each subframe with its own CRC

and allow retransmission of a subframe rather than the entire frame.

  • The number of subframes can be negotiated between different devices. Once these

parameters are negotiated they stay the same during one session. This reduces the

  • verhead and these parameters need not be transmitted every frame or before each

subframe.

  • If errors occur at the receiving device, the receiving device will request from the

transmitting device the retransmission of only those subframes in error and not the entire MPDU. This will increase the overall efficiency and capacity of the system.

MPDU-1 Subframe 1 CRC-1 Subframe N Block ACK (corresp. to the N subframes)

SIFS

CRC-2 CRC-2 MPDU-2 MPDU-M

Preamble MAC & PHY Header

Subframe 2

slide-67
SLIDE 67

July 9, 2006

Ismail Lakkis, Tensorcom Slide 67

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Results

slide-68
SLIDE 68

July 9, 2006

Ismail Lakkis, Tensorcom Slide 68

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Assumptions

! Channel Bandwidth = 1720.32 MHz ! AWGN, CM13, CM23, CM31 (Golden Set) ! Omnidirectional antennas at both ends ! 50 ppm XTAL (±25 ppm @ each side) ! Simulation includes

  • Coarse/ fine frequency acquisiton & tracking
  • Channel estimation
  • Frequency domain MMSE Equalizer
  • Soft bit generation
  • TLDPC & RS decoding
slide-69
SLIDE 69

July 9, 2006

Ismail Lakkis, Tensorcom Slide 69

doc.: IEEE 802.15-0760-01-003c

Submission

Long Preamble Miss Detection & False Alarm

  • 18
  • 16
  • 14
  • 12
  • 10

5 10 15 20 25 EcN0dB Probability of Miss PM for a target PF = 1% AWGN CM13 CM31 CM23

  • 18
  • 16
  • 14
  • 12
  • 10

5 10 15 20 25 EcN0dB Probability of Miss PM for a target PF = 2% AWGN CM13 CM31 CM23

  • 18
  • 16
  • 14
  • 12
  • 10

5 10 15 20 25 EcN0dB Probability of Miss PM for a target PF = 3% AWGN CM13 CM31 CM23

  • 18
  • 16
  • 14
  • 12
  • 10

5 10 15 20 25 EcN0dB Probability of Miss PM for a target PF = 5% AWGN CM13 CM31 CM23

slide-70
SLIDE 70

July 9, 2006

Ismail Lakkis, Tensorcom Slide 70

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Results: AWGN

1 2 3 4 5 6 7 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

10

  • 2

EbN0dB BER SC/OFDM AWGN mode 4 mode 3 mode 2 mode 1 1 2 3 4 5 6 7 10

  • 5

10

  • 4

10

  • 3

10

  • 2

10

  • 1

10 EbN0dB PER SC/OFDM AWGN mode 4 mode 3 mode 2 mode 1

slide-71
SLIDE 71

July 9, 2006

Ismail Lakkis, Tensorcom Slide 71

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Results: CM13 (CP=0)

1 2 3 4 5 6 7 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

10

  • 2

EbN0dB BER SC/OFDM CM13 mode 4 mode 3 mode 2 mode 1 1 2 3 4 5 6 7 10

  • 5

10

  • 4

10

  • 3

10

  • 2

10

  • 1

10 EbN0dB PER SC/OFDM CM13 mode 4 mode 3 mode 2 mode 1

slide-72
SLIDE 72

July 9, 2006

Ismail Lakkis, Tensorcom Slide 72

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Results: CM31 (CP=64)

4 6 8 10 12 14 10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

10

  • 2

EbN0dB BER SC/OFDM CM31 mode 4 mode 3 mode 2 mode 1 4 6 8 10 12 14 10

  • 4

10

  • 3

10

  • 2

10

  • 1

10 EbN0dB PER SC/OFDM CM31 mode 4 mode 3 mode 2 mode 1

slide-73
SLIDE 73

July 9, 2006

Ismail Lakkis, Tensorcom Slide 73

doc.: IEEE 802.15-0760-01-003c

Submission

Simulation Results: CM23 (CP=64)

5 10 15 10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

10

  • 3

10

  • 2

EbN0dB BER SC/OFDM CM23 mode 4 mode 3 mode 2 mode 1 5 10 15 10

  • 4

10

  • 3

10

  • 2

10

  • 1

10 EbN0dB PER SC/OFDM CM23 mode 4 mode 3 mode 2 mode 1

slide-74
SLIDE 74

July 9, 2006

Ismail Lakkis, Tensorcom Slide 74

doc.: IEEE 802.15-0760-01-003c

Submission

Link Budget: AWGN (8%PER)

Assumptions

Radio Noise Figure 8.0 dB Tx Antnna Gain 6.0 dB Rx Antenna Gain 6.0 dB High Data Rate Implementation Loss 0.0 dB Medium/Low Data Rate Implementation Loss 0.0 dB

PARAMETERS value value value value Unit Transmitter Information Data Rate (Rb)

3967.962 2645.308 1511.605 755.802

Mbps Geometric mean [fg = sqrt(fmin x fmax] 60.000 60.000 60.000 60.000 GHz Bandwidth (BW) 1.7203 1.7203 1.7203 1.7203 GHz Spectral DensityLimit

  • 22.36
  • 22.36
  • 22.36
  • 22.36

dBm/MHz Tx Antenna Gain (GT) 6.0 6.0 6.0 6.0 dB Tx Average Power (PT) 10.00 10.00 10.00 10.00 dBm Receiver Rx Noise Figure Referred to the Antenna Terminal (NF) 8.0 8.0 8.0 8 dB Eb/N0 (8% PER) 5.5 4.8 2.9 2.3 dB Implementation Losses 0.0 0.0 0.0 0.0 dB Rx Antenna Gain (GR) 6.0 6.0 6 6 Sensitivity Propagation Loss Index 2 2 2 2 Path Loss at 1m (L1) 68.00 68.00 68.00 68.00 dB Minimum Rx Sensitivity Level (Smin)

  • 64.5
  • 67.0
  • 71.3
  • 74.9

dBm Link Margin (M) 1.0 1.0 1.0 1.0 dB Rx Power Caluclations Path Loss Ld = PR - (PT + GT + GR + M) 85.51 87.98 92.31 95.92 dB Range d(m) 7.51 9.97 16.41 24.86 m Different Modes

slide-75
SLIDE 75

July 9, 2006

Ismail Lakkis, Tensorcom Slide 75

doc.: IEEE 802.15-0760-01-003c

Submission

Link Budget: CM31 (8%PER)

Assumptions

Radio Noise Figure 8.0 dB Tx Antnna Gain 6.0 dB Rx Antenna Gain 6.0 dB High Data Rate Implementation Loss 0.0 dB Medium/Low Data Rate Implementation Loss 0.0 dB

PARAMETERS value value value value Unit Transmitter Information Data Rate (Rb)

3967.962 2645.308 1511.605 755.802

Mbps Geometric mean [fg = sqrt(fmin x fmax] 60.000 60.000 60.000 60.000 GHz Bandwidth (BW) 1.7203 1.7203 1.7203 1.7203 GHz Spectral DensityLimit

  • 22.36
  • 22.36
  • 22.36
  • 22.36

dBm/MHz Tx Antenna Gain (GT) 16.0 16.0 16.0 16.0 dB Tx Average Power (PT) 10.00 10.00 10.00 10.00 dBm Receiver Rx Noise Figure Referred to the Antenna Terminal (NF) 8.0 8.0 8.0 8 dB Eb/N0 (8% PER) 11.6 9.9 6.3 5.8 dB Implementation Losses 0.0 0.0 0.0 0.0 dB Rx Antenna Gain (GR) 16.0 16.0 16 16 Sensitivity Propagation Loss Index 2.5 2.5 2.5 2.5 Path Loss at 1m (L1) 68.00 68.00 68.00 68.00 dB Minimum Rx Sensitivity Level (Smin)

  • 58.4
  • 61.9
  • 67.9
  • 71.5

dBm Link Margin (M) 5.0 5.0 5.0 5.0 dB Rx Power Caluclations Path Loss Ld = PR - (PT + GT + GR + M) 95.41 98.88 104.91 108.47 dB Range d(m) 2.61 3.59 6.25 8.68 m Different Modes

slide-76
SLIDE 76

July 9, 2006

Ismail Lakkis, Tensorcom Slide 76

doc.: IEEE 802.15-0760-01-003c

Submission

PHY-SAP Throughput

  • Assumptions:

– MPDU (MAC frame body + FCS) length = 16384 Octets – SIFS = 2.5 µs – MIFS = 0.5 µs

3077 2020 1172 586 16384 Throughput @ 3968Mbps Throughput @ 2605Mbps Throughput @ 1512Mbps Throughput @ 756Mbps MPDU Length

slide-77
SLIDE 77

July 9, 2006

Ismail Lakkis, Tensorcom Slide 77

doc.: IEEE 802.15-0760-01-003c

Submission

Summary

! Dual-mode SC (Single Carrier) / OFDM for different classes of devices ! SC is the mode of choice for low complexity medium data rate ! OFDM is the modulation of choice of very high data rate ! Low-complexity interoperability common mode for interoperability between different devices/ networks ! Unified common frame format enabling a single HW supporting SC / OFDM ! Link Adaptation & Unequal Error Protection via low – complexity Structured Turbo LDPC, convolutional Codes / RS ! Balanced Channelization with multiple XTAL support