Project Duration Digital IC Project and Verification Dec 1st April - - PowerPoint PPT Presentation

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Digital IC‐Project and Verification Project Presentation

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Project Duration

• It might seem a long time to you but...

...our experience says its NOT

Dec 1st April 1st ~14 weeks Deadline Choose project

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Project Duration

• In week 2 you will give an initial project presentation

including

– project specification – time‐plan – exspected results

• 5 minutes plus discussion

Dec 1st April ~14 weeks Final presentation and report 1st presentation

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Project Definition Phase

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Practicalities

• Disk quota – 200MB

– for temporary storage /nobackup/”machine_name”/ create your own directory no backup and files can be deleted

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Design Issues

• Things to think about early on:

– Limit on chip memory – Keep the number of pads low,

• we don’t want

Chip Design

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Grading

• Performance during project and final design will be

graded

• Individual grading if necessary
• Projects have different classifications dependent on

project difficulty

• Higher classification may result in a higher grade
• Classification can be changed
• Several major revision (>2) of report will result in

degradation

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Projects

• Viterbi Decoder

– Reza Mejari

• Hardware Based Media player

– Yasser Sherazi

• Multiple Stream Radix‐2 FFT (4/5)

– Hemanth Prabhu

• Object Feature Extraction

– Isael Diaz

• RISC track

– Chenxin Zhang

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Viterbi Decoder‐Objectives ‐Reza Meraji

• You will design a decoder codes generated by 4‐state encoder.
• Learn the algorithm
• Develope a Matlab model
• Implement in VHDL
• Compare the results with Matlab model
• Verify on hardware

Design a functional decoder for the encoder above

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Viterbi Decoder‐Grading

• Grade: 3

Mandatory: Hard decision decoding + fixed block length + comparison with Matlab + report

• Grade: 4

Mandatory: Tasks for grade 3 + adjustable block length + soft decoding + optimization + high quality report

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Hardware Based Media player (3/4/5)

‐ Yasser Sherazi

• You will design a hardware based

stereo media player application.

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Grading

• Grade: 3

– analog stereo sound input and output sound on speakers. 10 different frequency bands on the VGA monitor for each channel.

• Grade: 4

– A keyboard based control panel that should be able to control the volume, balance and frequency attenuations or amplifications.

• Grade: 5

– Echo feature with a control system to change the echo duration for at least two different time periods. A preliminary report explaining how you have defined reconstruction of audio signal after filtering together with MATLAB and VHDL implementations is required for all tasks

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Object Feature Extraction (3/4) ‐ Isael Diaz

• Surveillance applications have been a major

development area for the last decade.

• Automated surveillance systems target a huge niche
• f opportunities in national security
• Todays technology is able to process information

within the camera. Object moving BG Subtraction Object Segmentation Feature Extraction Object tracking

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Multiple Stream Radix‐2 FFT (4/5)

‐ Hemanth Prabhu

• You will design a radix‐2 butterfly based

FFT, which can support up to 4 parallel data paths (streams).

• The FFT needs to support high throughput,

hence a pipeline architecture (SDF, MDF) is preferable.

• The multiple data paths needs to be

implemented efficiently to reduce area, by sharing hardware resources.

• The FFT also needs to be flexible and

support different FFT lengths (64~256).

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Mini‐MIPS project (4/5)

‐Chenxin Zhang

• 32‐bit RISC with a subset of MIPS instructions.
• Grading:

– Grade 4: Fully verified pipelined Mini‐MIPS. – Grade 5: I/O console, or extended instruction set,

• r memory hierarchy.
• Prerequisite course:

– EITF35 Introduction to Structured VLSI Design – EITF20 Computer Architecture

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Mandatory tasks

• Task 1: behavior modeling
• Task 2: synthesizable pipelined implementation
• Task 3: P&R in 130 nm CMOS
• Task 4: Verification in FPGA

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Own projects ‐Joachim Rodrigues

• Project abstract needs to be submitted.
• Prerequisite

– Grade 5 in EITF35 and ETI130 – Suitable idea

Joachim Rodrigues, EIT, LTH, Digital IC project and Verification jrs@eit.lth.se Projects

Project Selection

• Contact the supervisors if you have any

questions

• Send me an email with 1st/2nd choice of

project