Power Management in Power Management in Wireless SOCs SOCs - - PowerPoint PPT Presentation

Jan M. Rabaey Scientific Co-Director BWRC Director GSRC EECS Dept.

• Univ. of California, Berkeley

Power Management in Power Management in Wireless Wireless SOCs SOCs

With contributions of M. Sheets and H. Qin

The Leakage Challenge (1) The Leakage Challenge (1)

Year

2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16 0.2 0.4 0.6 0.8 1 1.2 20 40 60 80 100 120

Technology node[nm] Voltage [V] VTH VDD Technology node

2002 ’04 ’06 ’08 ’10 ’12 ’14 ’16

1 2 Year PDYNAMIC PLEAK Power [µW / gate] Subthreshold leak (Active leakage)

• T. Sakurai, ISSCC 03

The Leakage Challenge (2) The Leakage Challenge (2)

0.18 micron ~1000 samples

20X 30%

0.9 1.0 1.1 1.2 1.3 1.4 5 10 15 20

Normalized Leakage (Isb) Normalized Frequency

Source: S. Borkar, Intel

The Other Side of the Story: The Other Side of the Story: Leakage is good for you! Leakage is good for you!

10

• 2

10

• 1

10 10

1

0.2 0.4 0.6 0.8 1 ELeakage/ESwitching EOp / nominal E

Op ref

nominal parallel pipeline

Vth

ref-180mV

0.81Vdd

max

Vth

ref-95mV

0.57Vdd

max

Vth

ref-140mV

0.52Vdd

max

Optimal designs have high leakage (ELk/ESw ≈ 0.5) Must adapt to process variations and activity

Source: P. Source: P. Gelsinger Gelsinger (DAC04) (DAC04)

What to do about memory? What to do about memory? “The data retention voltage (DRV) “The data retention voltage (DRV)

0.2 0.4 0.6 0.8 1 10 20 30 40 50 60 Supply Voltage (V) 4KB SRAM Leakage C urrent (µA)

Measured DRV range

100 200 300 400 500 1000 2000 3000 4000 5000 6000 7000

DRV (mV)

Data obtained from 4K bytes SRAM test Data obtained from 4K bytes SRAM test-

• chip,

chip, implemented in 130 nm CMOS implemented in 130 nm CMOS

Calibrating for Process Variations Calibrating for Process Variations

Module

Most variations are systematic, and can be adjusted for at start-up time using one-time calibration!

• Relevant parameters: Tclock, Vdd, Vth
• Can be easily extended to include leakage-reduction and power-down in standby

Test Module Vbb

Test inputs and responses

Tclock

• Achieves the maximum power saving under technology limit
• Inherently improves the robustness of design timing
• Minimum design overhead required over

traditional design methodology

Vdd

Adaptive Body Biasing Adaptive Body Biasing

Source: P. Gelsinger (DAC04)

Introducing “Power Domains ( Introducing “Power Domains (PDs PDs)” )”

Similar in Concept to “Clock Domains”, but extended to include power-down (really!) and local supply and threshold voltage management.

Power source Active Power Network Active Power Network Load Load Load

• Dynamic voltages for

variable workload

• Power gating or shut-off for

leakage control

• Lifetime extension

exploiting battery attributes

• Noise management

Introducing “Power Domains ( Introducing “Power Domains (PDs PDs)” )”

Domain1 Power Scheduler/ Chip Supervisor Domain2 Domain3

Who is in charge?

Chip Supervisor (or Chip O/S)

• Maintains global state and

perspective

• Maintains system timers
• Alerts blocks of important events

µ-coded state machine Event decoder System supervisor Alarm Table w/IDs Alarm Manager System Timewheel

=

Next Alarm Timer subsystem Power control bus

Power control msgs System status msgs Functional units

A Case Study A Case Study — —

Protocol Processor for Wireless Sensor Networks Protocol Processor for Wireless Sensor Networks

Energy train DLL (MAC) App/UI Network Transport Baseband RF (TX/RX) Sensor/actuator interface Locationing Aggregation/ forwarding User interface Sensor/ actuators Antenna Chip Supervisor Reactive radio

Target: < 50 µW average “Charm” Processor

LocalHW MAC DW8051

256 DATA

Interconnect network

ADC 4kB XDATA 16kB CODE

PHY Chip Supervisor SIF SIF

ADC

Serial GPIO FlashIF

Serial

Charm Architecture Charm Architecture

• Reactive inter- and intra-chip signaling
• Aggressive Use of Power-Domains
• Chip Supervisor Manages Activity
• 1 V operational supply voltage
• 16 MHz Clock Frequency
• Simple processor aided

with dedicated accelerators

Call a Plumber…This Thing Leaks! Call a Plumber…This Thing Leaks!

Block Area (um2) Logic Memory Locationing 337990 39.9 DW8051 63235 8.2 2880.0 Interface 6098 0.8 Neighborlist 21282 2.5 13.5 Serial 2554 0.4 NetQ 6296 0.7 108.0 DLL 126846 17.4 13.5 Supervisor 51094 6.4 Total 76.3 3015.0

• Est. leakage @1V (uW)

64KB SRAM for SW code and data 30X the target power…just in leakage!!

Leakage vs. Supply Voltage Hey buddy, turn down the voltage! ~15X reduction

Data retention voltage

1/15 A * 0.3 V = 98% less leakage power

Gated Power Architecture Gated Power Architecture

• Vddhi – active mode voltage (nominal)
• Vddlo – standby mode voltage allows retention of state

vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd vdd gnd vvdd gnd vvdd gnd vvdd gnd vddhi gnd vddlo vddhi gnd vddlo vddhi gnd vddlo

VVDD GND VDD (1V) 300mV STBY

Power Switch Tile Power Switch Tile

• Tile is easily incorporated into standard design flow

– Cell has same pitch as std. cell library components – Switch tiles placed prior to other standard cells – One additional power strap added to power routing step

• Switch design can be independent of block size

– Built in buffer distributes driver circuitry – Enables creation of a buffer tree during STBY signal routing

Std cell height

STBY_buf

Delay / Leakage Tradeoff 1 1.5 2 2.5 3 3.5 10 20 30 40 50 Power switch width (um) Delay overhead 0.2 0.4 0.6 0.8 1 Delay overhead Leakage

Power Switch Sizing Power Switch Sizing

• Switch sizing enables trade-off between delay overhead and

leakage

– Delay scale normalized to un-gated design – Leakage scale normalized to case when switch size is 50 µm

• Timing slack determines delay requirement

– Control domains (DLL, processor) – tolerant of delay overhead – Datapath domains (locationing) – longer critical paths, less tolerant of delay overhead

• H. Qin

System Supervisor System Supervisor

• How to control block activation/deactivation?
• System supervisor centralizes power control

– Power subsystem – gates block power rails – Clock subsystem – gates block clocks – Timer subsystem – system time-wheel and wake-up timers

Power Network Interface Power Network Time subsystem Clock subsystem Power subsystem Command/ Event Dispatcher Power Domain A Power Domain B Power Domain C

Power Subsystem Power Subsystem

• Session controller – opens/closes sessions
• Connection table – holds connectivity masks and performs

port address translation

• Session table – keeps track of open sessions

Src Decoder Dest Decoder Connection Table Session Table Session Controller

connection mask

To/From Dispatcher SYSCLK

Charms Sub Charms Sub-

• blocks and Connectivity

blocks and Connectivity

DLL Controller (DW8051) Sensor Interface Serial Neighborlist Locationing Network Queues

I2C SPI RS-232 A A A B

Baseband

RF-frontend C D A B D E B B C A B A C E A A

Block Port A Port B Port C Port D Port E BB DLL DLL NETQ BB LOC NL DW8051 DW8051 NETQ NL DLL SERIAL LOC DLL NL DW8051 NETQ DW8051 DLL NL DW8051 DLL LOC SERIAL DW8051

Connectivity grid

Power Session Table Power Session Table

Before a power domain can communication with a neighbor, it must first open a session Power policy: A power domain can sleep if…

1) It has closed all its sessions 2) No other domain has a session open with it 3) It wants to go to sleep

A ‘1’ in row i means that power domain i has an open a session with another domain A ‘1’ in column k means that another domain

• pened a session with domain k

A ‘1’ in entry (i, i) is domain i's self-sleep bit

Session Table

can_sleep(i) = reduction_nor(row i) and can_sleep(i) = reduction_nor(row i) and reduction_nor(col reduction_nor(col i) i)

Src Domain Dest Domain

1 1 ... ... 1 1 1 1

Clocking Subsystem Clocking Subsystem

• Low frequency external clock (32 KHz)
• Generated, switchable, higher frequency clock (16 MHz)
• Two clocks are made phase-synchronous using DLL
• Control signals are generated by system supervisor

RINGOSC_EN

16 MHz Clock generator

REF_CLK_ROOT SYS_CLK_ASYNC REF_CLK_PIN

IBUF (pad)

REF_CLK_ROOT

N-stage chain (N ev en)

SYS_CLK_ASYNC Clock tree Clock tree

Variable delay line Priority encoder + digital controller

TIMERCLK SYSCLK

Parallel phase detector M-stage delay line

M

DETECT REF_CLK_CLOCKMAN

Phase synchronous

SYS_CLK_ROOT

Timer Subsystem Timer Subsystem

• Centralized system time-wheel

– Blocks schedule wake-up alarms – Eliminates other large counters so blocks can sleep – Allows power domains to sleep

• Very low switching activity factor

– SYSCLK is disabled during deep sleep – Serial (ripple) comparison starting with MSB

alarm_time

Free-running Counter

=

Alarm Entry #0 Alarm Entry #1 Alarm Entry #N-1

new_alarm

Alarm Scheduler

beep_beep

Alarm Manager System Time-wheel

To/From Dispatcher TIMERCLK SYSCLK

Wireless Sensor Network Protocol Processor Wireless Sensor Network Protocol Processor

In fab

µWs Standby Power < 1 mW On_Power 3mm x 2.75mm = 8.2 mm2 Chip Size 0.13µ CMOS Technology 1V(High) –0.3V(Low) Core Supply Voltages 68Kbytes On Chip memory 16MHz(Main), 1MHz(BB) Clocks Freqs 62.5K gates Gate Count 3.2M Transistor Count

64K memory

DW8051 µc

Base Band

Serial

I nterface

GPI O

I nterface

Locationing Engine

Neighbor List System Supervisor

DLL

Network Queues

Voltage Conv

A Longer Term Perspective: A Longer Term Perspective: On chip power generation and conversion networks On chip power generation and conversion networks

Anchor Spring flexure Comb fingers

Energy generation and conversion network Energy Source 1 Energy Source 2 Conversion Network 1 Conversion Network 2 Reservoir 1 (capacitor) Reservoir 2 (microbattery)

Micro-battery Electrostatic MEMS vibration converters

Summary and Perspectives Summary and Perspectives

• Active and static power

management is leading to a fundamental change in the concept of power distribution

• n a chip
• Power domains locally

manage and trade-off performance, leakage and process variance

• System supervisors giving

new meaning to the term OS

• Towards “PGE on a chip”