PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 TELECOMMUNICATION - - PowerPoint PPT Presentation

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PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 TELECOMMUNICATION - - PowerPoint PPT Presentation

PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 TELECOMMUNICATION SYSTEMS Monday, 14 November 2016 LINKING DIGITAL TELEPHONE EXCHANGES Clock THIKA Generator 30 Channel PCM E1 30 Channel PCM E1 30 Channel PCM-E1 NAKURU NAIROBI


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SLIDE 1

PLESIOCHROUNOUS DIGITAL HIERARCHY

ETI 2506 – TELECOMMUNICATION SYSTEMS Monday, 14 November 2016

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SLIDE 2

NAIROBI NAKURU THIKA MOMBASA

Clock Generator Clock Generator Clock Generator Clock Generator

30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1

LINKING DIGITAL TELEPHONE EXCHANGES

DESIGN ISSUES IN DIGITAL TRANSMISSION SYSTEMS

  • 1. How to ensure that the clock generators are synchronized
  • 2. How to support more traffic, i.e > 30 channels
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SLIDE 3

Plesiochronous telecommunication system is one where different parts of the system are almost, but not quite, perfectly synchronised.

PLESIOCHRONOUS SYSTEM

NAIROBI NAKURU THIKA MOMBASA

Clock Generator Clock Generator Clock Generator Clock Generator

30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1

2.048,000 ±3 𝑞𝑞𝑛 2.048,000 ±4 𝑑𝑞𝑡 2.048,000 ±2 𝑞𝑞𝑛 2.048,000 ±5 𝑞𝑞𝑛

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SLIDE 4
  • 1. The 24 channel PCM system (T1) is the primary
  • rder of Digital Multiplex System.
  • 2. If it is necessary to transmit more than 24 channels,

the system is build-up as in the “Plesiochronous Digital Hierarchy (PDH)”

PDH MULTIPLEX SYSTEM - NORTH AMERICA

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SLIDE 5

TI MUX T2 MUX T3 MUX T4 MUX

1 24 Four 1.544Mb/s Inputs 1 4

Seven 6.312 Mb/s inputs

1 7

1 6

PDH MULTIPLEX SYSTEM - NORTH AMERICA

Six 44.736 Mb/s inputs

64kb/s 1.544 Mb/s 6.312 Mbits/s

44.736 Mbits/s 274.176 Mbits/s

Twenty Four 64 kb/s inputs T1 T1 T1 T1 T2 = 4T1 EO-2 E0-3 EO-4 EO-1 ASC

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SLIDE 6

PDH MULTIPLEX SYSTEM - NORTH AMERICA

  • 1. Second order multiplexing (T2): Four primary systems

(24-channle each) are combined, multiplexed, to form an

  • utput having 96 channels.
  • 2. Third order Multiplexing (T3): Seven 96 channel

systems are multiplexed to give an output of 672- channels. 3. Fourth order Multiplexing (T4): Six 672 – channels systems are multiplexed to give an output of 4032 channels -

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SLIDE 7

SECOND ORDER - DS2 PDH (1.544 TO 6.312 MB/S)

  • 1. The 6.312-Mb/s output of a second order (DS2) Multiplexer is

created by multiplexing four first order (DS1) multiplexing

  • utputs.
  • 2. This is done by interleaving the bit stream of the four primary

systems.

  • 3. Each individual bit stream is called the “tributary”.

T2 MUX

1 4

6.312 Mbits/s

Four tributaries DS2 each at 1.544 Mb/s

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SLIDE 8

E1 MUX E2 MUX E3 MUX E4 MUX

1 32 Four 2.048Mbits/s Inputs 1 4 4

64kb/s 2.048 Mb/s 8.44 Mbits/s

34.368 Mbits/s 138.264 Mbits/s

Thirty two 64 kb/s inputs Four 8.44Mbits/s Inputs 1 Four 34.368Mbits/s Inputs 1 4

EUROPEAN PDH

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SLIDE 9

The multiplexing of several tributaries can be achieved a) Bit by bit multiplexing, i.e bit interleaving b) Word by word multiplexing or byte interleaving

INTERLEAVING

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SLIDE 10

COMPARISON OF BIT AND BYTE INTERLEAVING

Byte interleaving sets some restraints on the frame structure of the tributaries and require more memory storage. Bit interleaving is much simpler because it is independent

  • f frame structure and also requires less memory capacity.
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SLIDE 11

APPLICATION OF BIT INTERLEAVING

  • 1. Bit interleaving is used in T1 and E1 systems.
  • 2. A typical 6.312 Mb/s plesichronous multiplexer

has four primary (DS1) MUX, each having an

  • utput of 1.544 Mb/s, bit interleaved to form the

next level in hierarchy.

  • 3. Note that this output rate of 6.312 Mb/s is not

exactly four times the tributary bit rate of 1.544 Mb/s.

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SLIDE 12

BIT STUFFING IN PDH

Bit stuffing (also called positive justification) is the insertion of non information bits into data. Bit stuffing is used in PDH to account for the small variations of the tributaries data rates about the nominal value.

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SLIDE 13

PDH MUX Europe

  • In summary, the positive stuffing method involves

the canceling of a clock pulse assigned to a particular tributary in some of the frames in order to coordinate the timing of the plesiochronous tributaries into a multiplexed output.

  • Random spaces are therefore created in the frame,

as well as periodic spaces. In the periodic spaces frame alignment word bits service bits, and stuffing control bits are inserted. The tributary information bits are inserted in the random spaces in the absence of stuffing, or logic 1 is used when stuffing taken place.