PLESIOCHROUNOUS DIGITAL HIERARCHY
ETI 2506 – TELECOMMUNICATION SYSTEMS Monday, 14 November 2016
PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 TELECOMMUNICATION - - PowerPoint PPT Presentation
PLESIOCHROUNOUS DIGITAL HIERARCHY ETI 2506 TELECOMMUNICATION SYSTEMS Monday, 14 November 2016 LINKING DIGITAL TELEPHONE EXCHANGES Clock THIKA Generator 30 Channel PCM E1 30 Channel PCM E1 30 Channel PCM-E1 NAKURU NAIROBI
ETI 2506 – TELECOMMUNICATION SYSTEMS Monday, 14 November 2016
NAIROBI NAKURU THIKA MOMBASA
Clock Generator Clock Generator Clock Generator Clock Generator
30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1
DESIGN ISSUES IN DIGITAL TRANSMISSION SYSTEMS
Plesiochronous telecommunication system is one where different parts of the system are almost, but not quite, perfectly synchronised.
NAIROBI NAKURU THIKA MOMBASA
Clock Generator Clock Generator Clock Generator Clock Generator
30 Channel PCM – E1 30 Channel PCM – E1 30 Channel PCM-E1
2.048,000 ±3 𝑞𝑞𝑛 2.048,000 ±4 𝑑𝑞𝑡 2.048,000 ±2 𝑞𝑞𝑛 2.048,000 ±5 𝑞𝑞𝑛
the system is build-up as in the “Plesiochronous Digital Hierarchy (PDH)”
TI MUX T2 MUX T3 MUX T4 MUX
1 24 Four 1.544Mb/s Inputs 1 4
Seven 6.312 Mb/s inputs
1 7
1 6
Six 44.736 Mb/s inputs
64kb/s 1.544 Mb/s 6.312 Mbits/s
44.736 Mbits/s 274.176 Mbits/s
Twenty Four 64 kb/s inputs T1 T1 T1 T1 T2 = 4T1 EO-2 E0-3 EO-4 EO-1 ASC
(24-channle each) are combined, multiplexed, to form an
systems are multiplexed to give an output of 672- channels. 3. Fourth order Multiplexing (T4): Six 672 – channels systems are multiplexed to give an output of 4032 channels -
created by multiplexing four first order (DS1) multiplexing
systems.
T2 MUX
1 4
6.312 Mbits/s
Four tributaries DS2 each at 1.544 Mb/s
E1 MUX E2 MUX E3 MUX E4 MUX
1 32 Four 2.048Mbits/s Inputs 1 4 4
64kb/s 2.048 Mb/s 8.44 Mbits/s
34.368 Mbits/s 138.264 Mbits/s
Thirty two 64 kb/s inputs Four 8.44Mbits/s Inputs 1 Four 34.368Mbits/s Inputs 1 4
The multiplexing of several tributaries can be achieved a) Bit by bit multiplexing, i.e bit interleaving b) Word by word multiplexing or byte interleaving
Byte interleaving sets some restraints on the frame structure of the tributaries and require more memory storage. Bit interleaving is much simpler because it is independent
Bit stuffing (also called positive justification) is the insertion of non information bits into data. Bit stuffing is used in PDH to account for the small variations of the tributaries data rates about the nominal value.