IDEA 2015
Investigating Dataflow in Embedded computing Architecture
Pipelined Scheduling of Acyclic SDF Graphs using SMT Solvers
- P. Tendulkar, P. Poplavko, J. Maselbas, and O. Maler
Pipelined Scheduling of Acyclic SDF Graphs using SMT Solvers P. - - PowerPoint PPT Presentation
IDEA 2015 Investigating Dataflow in Embedded computing Architecture Pipelined Scheduling of Acyclic SDF Graphs using SMT Solvers P. Tendulkar, P. Poplavko, J. Maselbas, and O. Maler Verimag Lab (CNRS, University of Grenoble), France
Kalray MPPA256, Tilera GX, ST Micro P2012/Shtorm
model-checking (UPPAAL,…), ILP (lpsolve,…), SMT (Z3, …), etc…
23-Jan-15 Peter Poplavko / Verimag, Grenoble 1
23-Jan-15 Peter Poplavko / Verimag, Grenoble 2
PIPELINING : <
23-Jan-15 Peter Poplavko / Verimag, Grenoble 3
vA, vB – actors atomic software subroutines
instances (copies) of actor subroutines
Thread T -- in general, must be multi-thread A__B : new FIFO; procedure A is SubroutineA (A__B); -- actor vA procedure B is SubroutineB (A__B); -- actor vB k : Integer; begin for k in 1 . . ∞ loop A(1); A(2); B(1); -- uA1 uA2 uB1 end loop end
23-Jan-15 Peter Poplavko / Verimag, Grenoble 4
EXP tasks
= A ∪ B; A = uA1, uA2,uA3
start time of k-th execution of task u
u , + = u , + free variables per task O (EXP)
= 1 O (EXP)
23-Jan-15 Peter Poplavko / Verimag, Grenoble 5
23-Jan-15 Peter Poplavko / Verimag, Grenoble 6
23-Jan-15 Peter Poplavko / Verimag, Grenoble 7
, = +
23-Jan-15 Peter Poplavko / Verimag, Grenoble 8
+ +,,
uB1 uB2
B
23-Jan-15 Peter Poplavko / Verimag, Grenoble 9
23-Jan-15 Peter Poplavko / Verimag, Grenoble 10
C
B A C B A
23-Jan-15 Peter Poplavko / Verimag, Grenoble 11
23-Jan-15 Peter Poplavko / Verimag, Grenoble 12
(a) unfolding [Legriel ECRTS’11] (b) modulo scheduling, e.g. [Lombardi CPAIOR’11] SMT encoding : e.g. our tech rep. [TR-2014-5]
23-Jan-15 Peter Poplavko / Verimag, Grenoble 13
23-Jan-15 Peter Poplavko / Verimag, Grenoble 14
Core 0
C
time Core 1
B A C B A
= + . + + + − ≤