Photon Detector Electronics: Ganging Scenarios Zelimir Djurcic, - - PowerPoint PPT Presentation

Photon Detector Electronics: Ganging Scenarios

Zelimir Djurcic, Patrick De Lurgio, Gary Drake, Michael Oberling

Argonne National Laboratory

DUNE Photon Detection Workshop, May 17-18 2016

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• Several Ganging scenarios have been suggested
• Motivation: Reduce channel cost
• Besides cost, there are other aspects of system design that can impact the

deployment and operation of a system, including: electronics performance, complexity, risk, and reliability

• Cost also has two aspects: development cost (engineering) and production, which
• ften play off against each other.
• This talk is an attempt to analyze the scenarios in a relative way
• The scenarios considered are:
• Baseline Design: Gang 3 SiPMs together passively on the SiPM board
• Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on

the SSP board and add an intermediate active summer, possibly at the warm interface

• Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on

the SiPM board and add active summer at receiving end in the SSP

• Alternative Design #4: Cold Summing Circuits
• Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the

cable plant, and change the SSP for lower performance, higher channel count

SiPM Ganging Scenarios

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• Baseline Design: Gang 3 SiPMs together passively on the SiPM board

SiPM Ganging Scenarios

Existing SSP Electronics With New connectors

4 Groups 3 SiPMs Each CAT6a Cable 4 Shielded Twisted Pairs HV Power Each ch SSP Power

ADC ADC ADC ADC (12) Readout Channels Per Module

• Baseline Design: Gang 3 SiPMs together passively on the SiPM board (Cont.)

SiPM Ganging Scenarios (Cont.)

• Simple system design
• Avoids intermediate infrastructure
• Reduces cable plant & connectors
• Handles signals on cables properly
• Efficient in biasing SiPMs

from the SSP

• Provides good capability for

diagnostics  Charge Injection

• Requires modest change to SSP for

the new connectors

• Reduces channel cost by X3 of

current (already in the cost est.)

• Degrades S/N by 30%, & increases

decay by a factor of ~X2

• Large capacitance of the source may

need impedance compensation at source

• Does not allow for other cost-saving

measures (SSP redesign)

• Increased single point failures

 Bottom line: We think that we can make this work, but it is at the performance limit  R&D: Minimal, with limited changes to SSP for the new cable plant, ~ a few weeks of engineering  Production cost: Moderate, without further improvements to SSP

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• Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively
• n the SiPM board and add an intermediate active summer, possibly at the warm

interface

SiPM Ganging Scenarios (Cont.)

New Intermediate Summer Module

4 Groups 3 SiPMs Per Group CAT6a Cable 4 Shielded Twisted Pairs HV Power Each ch ? Summer Module Power

ADC

HV Power Each ch ? SSP Power

Existing SSP Electronics With New connectors?

• Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively
• n the SiPM board and add an intermediate active summer (Cont.)

SiPM Ganging Scenarios (Cont.)

 Bottom line: Poor from a system perspective, modest R&D, significant worries about performance  R&D: Development of high-performance Summing Module, new cable plant, minimal changes to SSP ~5 man-months of engineering  Production cost: SSPs read out 144 ch SiPMs, but have cost of Summing Modules

• Requires modest change to SSP for the

new connectors

• Have 2 cable termination problems
• Complex system design
• Must have intermediate infrastructure
• Increases cable plant & connectors
• Inefficient in biasing SiPMs

from the SSP

• Poor capability for diagnostics
• Requires development costs

(Comparison to original cost-saving R&D?...)

• Additional signal processing will add

noise, and reduce precious S/N headroom further

• Circuits amplify & sum noise from cable
• Summing circuits are hard to implement

without losing bandwidth

• Significant increase of single point

failures

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• Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively
• n the SiPM board and add active summer at receiving end in the SSP

SiPM Ganging Scenarios (Cont.)

New SSP Electronics With New connectors

4 Groups 3 SiPMs Per Group CAT6a Cable 4 Shielded Twisted Pairs

ADC

HV Power Each ch SSP Power (12) Readout Channels Per Module

• Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively
• n the SiPM board and add active summer at receiving end in the SSP (Cont.)

SiPM Ganging Scenarios (Cont.)

• Simple system design
• Avoids intermediate infrastructure
• Reduces cable plant & connectors
• Handles signals on cables properly
• Efficient in biasing SiPMs

from the SSP

• Provides good capability for diagnostics

 Charge Injection

• Requires SSP redesign to add summing

circuits  Development costs (Compare to original cost-saving R&D?...)

• Additional signal processing will add

noise, and reduce precious S/N headroom further

• Circuits amplify & sum noise from cable
• Summing circuits are hard to implement

without losing bandwidth

• Modest increase in single point failures

 Bottom line: Good from a system perspective, modest R&D, but worries about performance  R&D: Development of high- performance Summing Circuits for the SSP, new cable plant ~3 man-months of engineering  Production cost: SSPs read out 144 ch SiPMs, but have more circuitry

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• Alternative Design #4 – Cold Summing Circuits

SiPM Ganging Scenarios (Cont.)

Matched Individual SiPMs,12 per Module Summed into M Circuits CAT6a Cable 4 Shielded Twisted Pairs HV Power Each ch SSP Power

ADC ADC ADC (12) Readout Channels Per Module Existing SSP Electronics With New connectors

Summer Power

Sum N

• Alternative Design #4 – Cold Summing Circuits (Cont.)

SiPM Ganging Scenarios (Cont.)

• Moderate system design
• Moderate intermediate infrastructure
• Good cable plant & connectors
• Handles signals on cables properly
• Biasing SiPMs could be done

from the SSP

• Requires modest change to SSP

for the new connectors

• Best way to handle SiPM signal

processing – amplifier close, no cable

• Good noise performance- Amplify signal

before driving onto the cable

• Requires external power supply for the

cold electronics

• May require other control signals?
• Requires mech support on the detector
• Reduced capability for diagnostics
• Requires development costs

(But already started at IU...)

• Summing circuits are hard to implement

without losing bandwidth

• Significant risk of single point failures

 Bottom line: Good from a system perspective, modest R&D, should have good performance  R&D: New cable plant + cold, high- performance Summing Circuits, ~4 man-months of engineering  Production cost: SSPs read out 144 SiPMs, but have cold electronics

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• Original proposal – SSP Redesign: Gang 3 SiPMs together passively, change

the cable plant, and change the SSP for lower performance, higher channel count

SiPM Ganging Scenarios

Existing SSP Electronics With New connectors

4 Groups 3 SiPMs Each CAT6a Cable 4 Shielded Twisted Pairs HV Power Each ch SSP Power

(64) Readout Channels Per Module Commercial ASIC

• Original proposal – SSP Redesign: Gang 3 SiPMs together passively, new

cable plant, modify SSP for lower performance, higher channel count (Cont.)

SiPM Ganging Scenarios (Cont.)

• Simple system design
• Avoids intermediate infrastructure
• Minimizes cable plant & connectors
• Handles signals on cables properly
• Efficient in biasing SiPMs

from the SSP

• Provides good capability for

diagnostics  Charge Injection

• Reduces channel cost by ~X15 of

current

• More closely resembles what might

be needed for DUNE

• Requires significant change to SSP
• Requires some R&D
• Degrades S/N by 30%, & increases

decay by a factor of ~X2

• Large capacitance of the source may

need impedance compensation at source  Bottom line: This would be the most appropriate path for DUNE  R&D: Major changes to SSP ~ 6 months of engineering  Production cost: SSPs read out 192 SiPMs

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Summary

• How to navigate the complex parameter space?

System attributes considered:

• Performance Benefits
• System Complexity
• Risk
• R&D requirements
• Production Costs

Disclaimer: The following are my personal opinions as to the

relative ranking of the different scenarios for these attributes. You are free to challenge them or rank them yourselves… It is meant to be provocative, but also point out the different issues with deciding on an architecture…

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Summary I

• 5 Scenarios, grouped by Performance Benefits

1. Alternative Design #4 – Cold Summing Circuits 2. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 3. Baseline Design: Gang 3 SiPMs together passively on the SiPM board 4. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 5. Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SiPM board and add an intermediate active summer, possibly at the warm interface

Best Performance Least Performance

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Summary II

• 5 Scenarios, grouped by System Complexity

1. Baseline Design: Gang 3 SiPMs together passively on the SiPM board 2. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 3. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 4. Alternative Design #4: Cold Summing Circuits 5. Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SSP board and add an intermediate active summer, possibly at the warm interface

Least Complex Most Complex

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Summary III

• 5 Scenarios, grouped by Risk

1. Baseline Design: Gang 3 SiPMs together passively on the SiPM board 2. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 3. Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SSP board and add an intermediate active summer, possibly at the warm interface 4. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 5. Alternative Design #4: Cold Summing Circuits

Least Complex Most Complex

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Summary IV

• 5 Scenarios, grouped by R&D Requirements

1. Baseline Design: Gang 3 SiPMs together passively on the SiPM board 2. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 3. Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SiPM board and add an intermediate active summer, possibly at the warm interface 4. Alternative Design #4: Cold Summing Circuits 5. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the SiPM plant, and change the SSP for lower performance, higher channel count

Minimal R&D Significant R&D

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Summary V

• 5 Scenarios, grouped by Production Costs

1. Original Proposal – SSP Redesign: Gang 3 SiPMs together passively, change the cable plant, and change the SSP for lower performance, higher channel count 2. Baseline Design: Gang 3 SiPMs together passively on the SiPM board 3. Alternative Design #3 – Summing on SSP: Gang 3 SiPMs together passively on the SiPM board and add active summer at receiving end in the SSP 4. Alternative Design #4: Cold Summing Circuits 5. Alternative Design #2 – Summer Module: Gang 3 SiPMs together passively on the SiPM board and add an intermediate active summer, possibly at the warm interface

Least Expensive Most Expensive

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Overall

• How to navigate the complex parameter space?
• Performance Benefits
• System Complexity
• Risk
• R&D requirements
• Production Costs

Algorithm: 25 –  wi * (Rank)i where wi = 1