SLIDE 3 High-Speed DACs Have DDSs Inside
3
NCO
11675-002
SDIO SCLK CS IRQ RESET SYNCOUT0– SYNCOUT0+ PROTECT_OUT1 PROTECT_OUT0
DAC PLL SERDES PLL POWER-ON RESET SERIAL I/O PORT CONFIG REGISTERS CLK_SEL PLL_CTRL DACCLK PLL_LOCK SYNCHRONIZATION LOGIC DAC ALIGN DETECT HB1
TXEN0 TXEN1 SERDIN7± VTT SERDIN0±
CLOCK DATA RECOVERY AND CLOCK FORMATTER
SYNCOUT1+ SYNCOUT1–
REF AND BIAS
I120 SYSREF+ SYSREF– SDO
HB3 HB2 DACCLK
OUT3+ OUT3–
INV SINC
fDAC
÷4, ÷8 NCO COMPLEX MODULATION PHASE ADJUST Q-GAIN I-GAIN SYSREF Rx
CLK+ CLK–
MODE CONTROL DACCLK CLK Rx HB3 HB2 HB1 Q-OFFSET I-OFFSET HB1 HB3 HB2 MODE CONTROL HB3 HB2 HB1 FSC FSC
OUT2+ OUT2–
DACCLK
OUT1+ OUT1–
INV SINC
fDAC
÷4, ÷8 NCO COMPLEX MODULATION PHASE ADJUST Q-GAIN I-GAIN Q-OFFSET I-OFFSET FSC FSC
OUT0+ OUT0–
CLOCK DISTRIBUTION AND CONTROL LOGIC PDP1 PDP0
quadrature gain DC offset AD9144 JESD 204 B I Q I Q If no internal NCO
in FPGA
JESD204B suffices
- IP NCOs available
- Minimal NCO not
difficult to implement
A n a l
D e v i c e s , A D 9 1 4 4 d a t a s h e e t