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Ε Θ Ν Ι Κ Ο & Κ Α Π Ο ∆ Ι Σ Τ Ρ Ι Α Κ Ο Π Α Ν Ε Π Ι Σ Τ Η Μ Ι Ο ΕΘ ΘΝ ΝΙ ΙΚ ΚΟ Ο & & Κ ΚΑ ΑΠ ΠΟ Ο∆ ∆Ι ΙΣ ΣΤ ΤΡ ΡΙ ΙΑ ΑΚ ΚΟ Ο Π ΠΑ ΑΝ ΝΕ ΕΠ ΠΙ ΙΣ ΣΤ ΤΗ ΗΜ ΜΙ ΙΟ Ο Ε Α Θ Η Ν Ω Ν ΑΘ ΘΗ ΗΝ ΝΩ ΩΝ Ν Α Μ Ε Τ Α Π Τ Υ Χ Ι Α Κ Ο Τ Μ Η Μ Α Π Λ Η Ρ Ο Φ Ο Ρ Ι Κ Η Σ ΜΕ ΕΤ ΤΑ ΑΠ ΠΤ ΤΥ ΥΧ ΧΙ ΙΑ ΑΚ ΚΟ Ο Τ ΤΜ ΜΗ ΗΜ ΜΑ Α Π ΠΛ ΛΗ ΗΡ ΡΟ ΟΦ ΦΟ ΟΡ ΡΙ ΙΚ ΚΗ ΗΣ Σ Μ ΠΡΟΗΓΜΕΝΗ ΑΡΧΙΤΕΚΤΟΝΙΚΗ ΥΠΟΛΟΓΙΣΤΩΝ Ε Ρ Γ Α Σ Ι Α : P O W E R M A N A G E M E N T ΕΡ ΡΓ ΓΑ ΑΣ ΣΙ ΙΑ Α : : P PO OW WE ER R M MA AN NA AG GE EM ME EN NT T Ε Υπ . Καθηγητής : κ . Κ . Χαλάτσης Των : Κ ωστή Ελένης Μ 487 Ραπτοπούλου Κλεονίκης M5 1 5 Ψαρρα Τζανετίνας Μ 5 1 0 ΑΘΗΝΑ 2002 – 2003

Power Management 1. I ntroduction Over the last three decades a significant improvement in microprocessors’ performance has taken place. The reasons for the evolution in this sector are owed partly to the semiconductor technology scaling and partly to the innovations in computer architecture and in the accompanying software. In the first case, semiconductor technology scaling has resulted in larger numbers of smaller and faster transistors whereas in the second, microprocessors achieve performance greater than what would have been possible by technology scaling alone. In this essay we present some basic definitions relevant to power consumption. Hereafter, our emphasis is on the problem of dynamic and static power dissipation. We will also discuss some of the current power reduction techniques. 2. Architecture I mportance Before throwing light to the reasons of power dissipation (static and dynamic) we would like to lay particular stress on the importance of architectural decisions in this field. There are two main reasons why architecture is instrumental in boosting performance beyond technology scaling. First, technology scaling is often non- uniform. For example, the technologies used to build processors are optimized for speed, while technologies used to build main memories are mostly optimized for density. Without the help of new architectural techniques a smaller and faster processor would simply spend most of its time waiting for the relatively slower memory. Second, technology evolution makes it easier to reach higher integration by allowing us to pack more transistors on a chip of the same size. On the one hand processor generations deliver higher performance due to the usage of more transistors and higher frequencies. On the other hand there is a simultaneous increase in power requirements and density, which imposes stringent constraints for modern microprocessors. 1

Power Management It is clear thus that micro-architectural mechanisms will have to be (re)designed in order to focus on power concerns. To understand the opportunities for power optimizations at the micro-architectural level we first have to understand what are the sources of power dissipation in modern microprocessors. 3. Power Consumption Power consumption has become an important factor in microprocessor design. The situation is aggravating in multiprocessor systems such as servers where multiple processors are close to each other. An increase in power dissipation beyond current levels will have as a result disproportionate increases in cost as current power delivery and heat removal systems reach limits. Moreover, power constraints exist for mobile and embedded microprocessors. Maximization of battery life and heat removal are two problems that should be taken into consideration. The fact that power dissipation poses a significant performance limit has led to the consideration of power in the early stages of design process. Architects become more and more involved with this subject as the ability of circuit techniques to control dissipation have been rendered insufficient. As mentioned above, we are going to deal with two types of power consumption: dynamic power and static power. Dynamic power dissipation occurs whenever a transistor or wire changes voltage. As we will see, dynamic power dissipation is proportional to product of the number of devices changing value, of the speed of these changes (i.e., operating frequency) and the square of the voltage change. Reducing power dissipation is possible by reducing each of these factors. Power- aware micro-architectural techniques address the number of devices, and their switching speed, while taking performance into consideration. 2 P CV f (dynamic power equation) dyn = cc On the other hand with the term “leakage power” we refer to the power dissipated even when devices do not change values due to the imperfect nature of semiconductor-based transistors. In existing designs, leakage power is relatively small. Unfortunately, as we move towards smaller transistors and lower voltages, 2

Power Management there is a rapid increase in leakage power. Power-aware efforts in this area aim at cutting off power to devices while they are not being used. This is a challenging task as powering on and off devices requires some time and hence can severely impact performance. P V I = (static power equation) static cc leak The following figure (Figure 1) shows the increases in static and dynamic power for Intel’s past few technologies. Projecting these trends forward, static power dissipation will equal dynamic power dissipation within a few generations. Higher order effects unimportant today and aggressive dynamic power optimizations could cause the static and dynamic power contributions to become equal in as little as two generations. It is important thus, for architects, to be aware of how they may control static power dissipation in future technologies. Figure1. Treads in dynamic and static power dissipation showing increasing contribution of static power. 3

Power Management 4. Dynamic Power Management (DPM) Unlike bipolar technologies, where a majority of power dissipation is static, the bulk of power dissipation in properly-designed CMOS circuits is the dynamic charging and discharging of capacitances. Thus, a majority of the low power design methodology is dedicated to reducing this predominant factor of power dissipation. The following example underlines the factors that affect the dynamic power dissipation. For the simple inverter gate shown in Figure 2, it can be shown that a 2 low-to-high output transition draws C eff V Joules (energy) from the power supply, cc V . The high-to-low output transition dissipates the energy stored on the capacitor cc into the NMOS device. Given a frequency f of low-to-high output transitions, the 2 fC eff V power drawn from the supply is . This simple equation holds for more cc complex gates, and other logic styles as well, given a periodic input. Figure2. Dynamic Switching Power Dissipation C Accurate calculations for can be done as shown below. The basic capacitor eff elements are shown in Figure 2. The net loading capacitance, C , consists of gate eff capacitance of subsequent gate inputs attached to the inverter output, interconnect capacitance, and the diffusion capacitance on the drains of the inverter transistors. Test chips have shown that for 1.2 m ICs, the total capacitance is split roughly equally between these three types. As the minimum gate length scales down, though, interconnect capacitance will become dominant. 4

Power Management Usually, the value of f is a difficult number to quantify, as it is most likely not periodic, and is correlated with the input test vectors into the circuit. Without doing a switched-level circuit simulation, the best way to calculate f is to perform statistical analysis on the circuit to determine a mean value. Since dynamic switching power is the major component of overall power dissipation, the low-power design methodology concentrates on minimizing total capacitance, supply voltage, and frequency of transitions. Dynamic Power Management (DPM) is a design methodology that dynamically reconfigures an electronic system to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieve energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). The following model is used for dynamic power consumption: a : activity factor of node S x f : clock frequency 2 P afCV dyn = CC C : load capacitance of node S x 2 V : supply voltage (squared) CC C Based on the previous equation, an effective capacitance, , can be defined eff C eff = aC which combines the physical capacitance being switched, C, and the activity factor a. The effective capacitance can be found from simulation and measurements as: P dyn C = eff 2 fV CC For the DPM strategies, the input is the length of an upcoming idle period and the decision to be made is whether to transition to a lower power dissipation state while 5