PARR: Pin Access Planning and Regular Routing for Self- Aligned - PowerPoint PPT Presentation

PARR: Pin Access Planning and Regular Routing for Self- Aligned Double Patterning � Xiaoqing Xu, Bei Yu , Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan University of Texas at Austin �

Detailed Routing in Extreme Scaling ! Moore’s Law => Extreme Scaling 14nm NAND [Liebmann+,SPIE’13] 130nm NAND ! High pin density => Routability ! Less pitch => Printability

Challenge 1: Pin Accessibility � ! Access Point Selection ! Net ordering � !"## %2 ! !"## %1 ! !"## %1 ! !"## %2 ! $ ! (a) � (b) � M1!pin � Cell!boundary � M2!wire � Via � M3!wire � blocked!pin �

Challenge 2: Printability � ! 2-D routing vs 1-D routing › 2D: Larger design space; but restrictive design rules › 1D: better printability; but extra vias 2(D � 1(D � M1!pin � M3!wire � M2!wire � Via �

Previous Works ! Standard cell pin access [Xu+,ISPD’14] [Ye+,GLSVLSI’15] ! Pin access for placement [Taghavi+,ICCAD’10] ! Pin access for detailed routing [Ozdal,TCAD’09] [Nieberg+,DAC’11] [Qi+,ICCD’14] ! SADP-aware detailed routing [Mirsaeedi+,SPIE’11] [Gao+,ISPD’12] [Du+,DAC’13] [Liu+,DAC’14] ! Our contributions › Pin access planning and SADP-friendly 1-D routing › Handshake std-cell pin access with detailed routing to improve pin accessibility

Problem Formulation � ! Input : a netlist, pin access Look-Up Table (LUT) of the library and a set of design rules ! Output : design rule clean routing results ! Objective : perform the regular routing and design rule legalization simultaneously to achieve SADP-friendly routing results

Intra-Cell Pin Access [X. Xu+, ISPD’14] � ! Intra-cell pin access design ! Store in look-up table (LUT) (b) � (a) � M2!Rou<ng!track � M2!hit!point � M1!pin � M2!wire � M2!extension �

This Work: Inter-Cell Pin Access � ! is placed to the left of with the gap as % ! Intra-cell pin access for and interferes � viola<on! % ! M2!rou<ng!track � M2!hit!point! � M1!pin � M2!wires � Cell!boundary � M2!extension �

Local Pin Access Planning � ! Dynamic hit point scoring › Source pin (A) and target pin (B) › Assign higher score to the hit point with larger number of intra-cell pin access solutions A 0.3 0.4 0.7 0.5 B A

Global Pin Access Planning � ! Net weight for ordering – smaller order goes first › Order(net) = HPWL(net)*(1+ & *min{hp_s, hp_t} + Dcost(net) ! The term: min{hp_s, hp_t}- minimum # of hit points for source/target pins › Defer the nets with robust source and target pins ! The term Dcost(net)- deferring cost › Maintain the ' to ( path existence of of PAG › Preserve the pin accessibility of the remaining nets

Single Row Pin Access Graph (PAG) � ! Routed wires block some intra-cell pin access !"## %0 ! !"## %1 ! !"## %2 ! !"## %3 ! !"## %4 ! !"## % 5! routed!wire! blocked!intraAcell!pin!access! infeasible! ' ! ' ! ! ( ! ( ! …" …" …" …" …" …"

1-D Routing with Rule Legalization ! 1-D A* search › Forbidden via positions a 2 b 2 a 1 b 1

Trade-off � ! Vary deferring cost upper bound � 100.0%! 160! Rout.(%)! cpu(s)! 95.0%! 120! Rout.(%)! cpu(s) � 90.0%! 80! 85.0%! 40! 0! 1! 2! 3! 4! 5! Normalized!deferring!cost!upper!bound!

Routability Improvement � 100.0%! 75.0%! Rout. � 50.0%! 25.0%! 0.0%! ecc! efc! ctl! alu! div! top!

Wirelength Impact � 1E+6! 1E+4! WL*! 1E+2! 1E+0! ecc! efc! ctl! alu! div! top!

Via Number per Routed Net (V.p.n) � 4.0!! 3.0!! V.p.n! 2.0!! 1.0!! 0.0!! ecc! efc! ctl! alu! div! top!

Run Time Reduction � 1000! 100! CPU(s) � 10! 1! ecc! efc! ctl! alu! div! top!

Conclusion � ! Pin Accessibility Prediction › Intra-cell and inter-cell ! Local and Global Pin Access Planning ! 1-D routing patterns › Forbid the non-preferred direction Thank you! Q&A