PARR: Pin Access Planning and Regular Routing for Self- Aligned - - PowerPoint PPT Presentation

▶

Feb 07, 2024 319 likes •509 views

PARR: Pin Access Planning and Regular Routing for Self- Aligned Double Patterning Xiaoqing Xu, Bei Yu , Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan University of Texas at Austin Detailed Routing in Extreme Scaling ! Moores Law =>

SLIDE 1

Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan University of Texas at Austin

PARR: Pin Access Planning and Regular Routing for Self- Aligned Double Patterning

SLIDE 2

130nm NAND 14nm NAND [Liebmann+,SPIE’13]

Detailed Routing in Extreme Scaling

! Moore’s Law => Extreme Scaling ! High pin density => Routability ! Less pitch => Printability

SLIDE 3

Challenge 1: Pin Accessibility

! Access Point Selection ! Net ordering (a) (b)

!"##%1! !"##%2!

M3!wire Cell!boundary M2!wire blocked!pin

!"##%1! !"##%2! $!

M1!pin Via

SLIDE 4

Challenge 2: Printability

! 2-D routing vs 1-D routing

› 2D: Larger design space; but restrictive design rules › 1D: better printability; but extra vias

M3!wire M2!wire M1!pin Via

2(D 1(D

SLIDE 5

Previous Works

! Standard cell pin access [Xu+,ISPD’14] [Ye+,GLSVLSI’15] ! Pin access for placement [Taghavi+,ICCAD’10] ! Pin access for detailed routing [Ozdal,TCAD’09] [Nieberg+,DAC’11] [Qi+,ICCD’14] ! SADP-aware detailed routing [Mirsaeedi+,SPIE’11] [Gao+,ISPD’12] [Du+,DAC’13] [Liu+,DAC’14] ! Our contributions

› Pin access planning and SADP-friendly 1-D routing › Handshake std-cell pin access with detailed routing to improve pin accessibility

SLIDE 6

Problem Formulation

! Input: a netlist, pin access Look-Up Table (LUT)

f the library and a set of design rules

! Output: design rule clean routing results ! Objective: perform the regular routing and

design rule legalization simultaneously to achieve SADP-friendly routing results

SLIDE 7

Intra-Cell Pin Access [X. Xu+, ISPD’14]

! Intra-cell pin access design ! Store in look-up table (LUT) (a) (b)

M1!pin M2!extension M2!hit!point M2!wire M2!Rou<ng!track

SLIDE 8

This Work: Inter-Cell Pin Access

! is placed to the left of with the gap as % ! Intra-cell pin access for and interferes M1!pin M2!extension M2!hit!point! Cell!boundary M2!wires M2!rou<ng!track

%! viola<on!

SLIDE 9

Local Pin Access Planning

! Dynamic hit point scoring

› Source pin (A) and target pin (B) › Assign higher score to the hit point with larger number

f intra-cell pin access solutions

A B

A

0.7 0.5 0.4 0.3

SLIDE 10

Global Pin Access Planning

! Net weight for ordering – smaller order goes first

› Order(net) = HPWL(net)(1+&min{hp_s, hp_t} + Dcost(net)

! The term: min{hp_s, hp_t}- minimum # of hit

points for source/target pins

› Defer the nets with robust source and target pins

! The term Dcost(net)- deferring cost

› Maintain the ' to ( path existence of of PAG › Preserve the pin accessibility of the remaining nets

SLIDE 11

Single Row Pin Access Graph (PAG)

! Routed wires block some intra-cell pin access

!"##%1! !"##%2! !"##%0! !"##%3! !"##%4! !"##%5! routed!wire! '!

(! …" …" …" …" …" …" (! '! infeasible! blocked!intraAcell!pin!access!

SLIDE 12

1-D Routing with Rule Legalization

! 1-D A* search

› Forbidden via positions

a1 a2 b1 b2

SLIDE 13

Trade-off

! Vary deferring cost upper bound

40! 80! 120! 160! 85.0%! 90.0%! 95.0%! 100.0%! 0! 1! 2! 3! 4! 5!

cpu(s) Rout.(%)! Normalized!deferring!cost!upper!bound!

Rout.(%)! cpu(s)!

SLIDE 14

Routability Improvement

0.0%! 25.0%! 50.0%! 75.0%! 100.0%! ecc! efc! ctl! alu! div! top!

Rout.

SLIDE 15

Wirelength Impact

1E+0! 1E+2! 1E+4! 1E+6! ecc! efc! ctl! alu! div! top!

WL*!

SLIDE 16

Via Number per Routed Net (V.p.n)

0.0!! 1.0!! 2.0!! 3.0!! 4.0!! ecc! efc! ctl! alu! div! top!

V.p.n!

SLIDE 17

Run Time Reduction

1! 10! 100! 1000! ecc! efc! ctl! alu! div! top!

CPU(s)

SLIDE 18

Conclusion

! Pin Accessibility Prediction

› Intra-cell and inter-cell

! Local and Global Pin Access Planning ! 1-D routing patterns