Global routing Global routing Global routing Global routing Bill - - PowerPoint PPT Presentation

Global routing Global routing Global routing Global routing

Bill Swartz Bill Swartz InternetCAD.com InternetCAD.com InternetCAD.com InternetCAD.com

Disclaimer Disclaimer Disclaimer Disclaimer

Paper written in 5 days

Paper written in 5 days

Please forgive any errors, typos,

Please forgive any errors, typos,

• missions and possible legal
• missions and possible legal
• missions, and possible legal
• missions, and possible legal

transgressions transgressions

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Backgro nd Backgro nd Background Background

TimberWolf Systems / InternetCAD.com

TimberWolf Systems / InternetCAD.com f d i 1994 f d i 1994 formed in 1994. formed in 1994.

Concentrated on producing high quality

Concentrated on producing high quality Concentrated on producing high quality Concentrated on producing high quality results for small chips and block designs. results for small chips and block designs.

Claim to fame: 486, Pentium series, Alpha,

Claim to fame: 486, Pentium series, Alpha, and Centrino and Centrino and Centrino and Centrino

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B t B t But… But…

One company no longer uses the product

One company no longer uses the product d l i t d l i t and one no longer exists… and one no longer exists…

Business is now predominantly DRAM

Business is now predominantly DRAM Business is now predominantly DRAM. Business is now predominantly DRAM.

Wrote grouter (2D) and igrouter (3D).

Wrote grouter (2D) and igrouter (3D). H l d it Ti b W lfGR d SGGR H l d it Ti b W lfGR d SGGR

Helped write TimberWolfGR and SGGR.

Helped write TimberWolfGR and SGGR.

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O tline O tline Outline Outline

• Introduction

Introduction A li i A li i

• Applications

Applications

• Previous work / state

Previous work / state-of

• f-the art

the art

• Previous work / state

Previous work / state-of

• f-the art

the art

• Advanced objectives and requirements

Advanced objectives and requirements j q j q

• Alternative methodologies

Alternative methodologies

• Itools global router

Itools global router

• Summary

Summary

• Summary

Summary

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Ph sical Design Stages Ph sical Design Stages Physical Design Stages Physical Design Stages

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Global ro ting definition Global ro ting definition Global routing definition Global routing definition

• Assign net segments to physical regions.

Assign net segments to physical regions. Assign net segments to physical regions. Assign net segments to physical regions.

• Model regions as a graph.

Model regions as a graph.

• Nets are embedded into graph

Nets are embedded into graph g p g p

• Minimize the total overflow on all global edges

Minimize the total overflow on all global edges

Global Bins Global Bins Cells Global Edges

(a)

Global Edges

(b)

From Pan M, Chu C.

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Cost function Cost function Cost function Cost function

∑ n W ) ( ∑

∈N n

n W ) (

B b b 1 B b P subject

c

≤ ≤ = 1 ,

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Global ro ting diffic lt Global ro ting diffic lt Global routing difficulty Global routing difficulty

• Easiest of three primary subtasks

Easiest of three primary subtasks F

• Fast

Fast

• Detail router can ignore global routing to

Detail router can ignore global routing to

• Detail router can ignore global routing to

Detail router can ignore global routing to complete design complete design

• Global routing is not necessary for

Global routing is not necessary for sufficiently small designs sufficiently small designs sufficiently small designs sufficiently small designs

• Negotiated detail router (Pathfinder) + A*

Negotiated detail router (Pathfinder) + A* g ( ) g ( ) search performs poor man's global routing search performs poor man's global routing

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Global and Detail Router Global and Detail Router Programs Programs

Combination of base, meta, and hierarchical Combination of base, meta, and hierarchical algorithms algorithms algorithms. algorithms. Base : how to route a single net or net segment Base : how to route a single net or net segment

Maze, pattern, line search, gridded, etc. Maze, pattern, line search, gridded, etc.

Meta : how to route a set of nets Meta : how to route a set of nets Meta : how to route a set of nets Meta : how to route a set of nets

Ripup and Reroute, Pathfinder, Graph Ripup and Reroute, Pathfinder, Graph-

• Based,

Based, Lagrange Relaxation Linear Programming Network Lagrange Relaxation Linear Programming Network Lagrange Relaxation, Linear Programming, Network Lagrange Relaxation, Linear Programming, Network Flows, etc. Flows, etc.

Hi hi l h t t t f i Hi hi l h t t t f i Hierarchical : how to route a set of regions Hierarchical : how to route a set of regions

Multilevel, channel Multilevel, channel-

• based methods, wire ordering

based methods, wire ordering

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(Groeneveld) (Groeneveld)

Detail Ro ting Meta Algorithms Detail Ro ting Meta Algorithms Detail Routing Meta Algorithms Detail Routing Meta Algorithms

Now appear in global routers

Now appear in global routers

Ripup and Reroute

Ripup and Reroute

Ripup and Reroute

Ripup and Reroute

Graph

Graph-

• based Conflict Removal

based Conflict Removal p

Congestion Negotiation (Pathfinder)

Congestion Negotiation (Pathfinder)

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The problem The problem The problem The problem

Shaded area keepouts; pins blue; fly-lines denote net connections p p y Single routing layer From Tatsuo Ohtsuki, “Layout Design and Verification” 1986

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, y g

Net 1 is blocked Net 1 is blocked Net 1 is blocked Net 1 is blocked

R t t 2 fi t Route net 2 first

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Net Net 2 is blocked is blocked Net Net 2 2 is blocked is blocked

O d i t ’t l bl Ordering nets won’t solve problem

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Rip p and Rero te Rip p and Rero te Ripup and Reroute Ripup and Reroute

Ripup and reroute net segments

Ripup and reroute net segments -

• not the

not the ti t! ti t! entire net! entire net!

Ripup of entire net does not work

Ripup of entire net does not work Ripup of entire net does not work. Ripup of entire net does not work.

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Rip p/Rero te Net 2 is blocked Rip p/Rero te Net 2 is blocked Ripup/Reroute: Net 2 is blocked Ripup/Reroute: Net 2 is blocked

Initial state Recursion depth 0 Recursion depth 0

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Rip p/Rero te Ro te net 2 Rip p/Rero te Ro te net 2 Ripup/Reroute: Route net 2 Ripup/Reroute: Route net 2

R t b i t 1’ t Route borrowing net 1’s segment Recursion depth 1

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Ripup/Reroute: Ripup net 1 Ripup/Reroute: Ripup net 1 p p p p p p p p segment segment

Recursion depth 0 Remove net 1 segments Recursion depth 0

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Rip p/Rero te Ro te net 2 Rip p/Rero te Ro te net 2 Ripup/Reroute: Route net 2 Ripup/Reroute: Route net 2

But we fail to route 1 Recursion depth 0

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Rip p/Rero te Backtrack Rip p/Rero te Backtrack Ripup/Reroute: Backtrack Ripup/Reroute: Backtrack

Back at start Recursion depth 0 Recursion depth 0

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Rip p/Rero te Ro te net 2 Rip p/Rero te Ro te net 2 Ripup/Reroute: Route net 2 Ripup/Reroute: Route net 2

Bl k i f il d t b i f t 1 Block previous failure and route borrowing from net 1 Recursion depth 1 Recursion depth 1

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Ripup/Reroute: Ripup net Ripup/Reroute: Ripup net1 1 p p p p p p p p segment segment

Prepare to route net 2 Recursion depth 0

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Ripup/Reroute: Ripup of segment Ripup/Reroute: Ripup of segment p p p p g p p p p g

• f net 2 to route net 1
• f net 2 to route net 1

Recursion depth 0 Routing succeeds for net 2 Recursion depth 0

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Ripup/Reroute: Routing Ripup/Reroute: Routing p p g p p g complete complete

Recursion depth 0 Routing succeeds for net 1

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Graph Graph based Initial conflicts based Initial conflicts Graph Graph-based : Initial conflicts based : Initial conflicts

Conflicts shown in orange

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Graph Graph-

• based: Alternative route

based: Alternative route p for net for net 1 1

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Graph Graph-based: Alternative based: Alternative Graph Graph based: Alternative based: Alternative candidate for net 2 candidate for net 2

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Graph Graph Based Conflict Graph Based Conflict Graph Graph Graph-Based: Conflict Graph Based: Conflict Graph

1 2 2

Alternative route

3 1 4 5

Alternative route

Each candidate route becomes a node in conflict graph Conflicting route candidates form edges Find set of nodes with no conflicting edges

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Graph Graph-

• based: Conflicts

based: Conflicts p resolved resolved

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Pathfinder Initial Conflicts Pathfinder Initial Conflicts Pathfinder: Initial Conflicts Pathfinder: Initial Conflicts

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Pathfinder Second Iteration Pathfinder Second Iteration Pathfinder: Second Iteration Pathfinder: Second Iteration

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Pathfinder Conflicts resol ed Pathfinder Conflicts resol ed Pathfinder: Conflicts resolved Pathfinder: Conflicts resolved

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Detail Routing Meta Algorithms Detail Routing Meta Algorithms Detail Routing Meta Algorithms Detail Routing Meta Algorithms

Relative Speed of Relative Speed of Relative Speed of Relative Speed of Convergence Convergence Weakness Weakness Easy Instance Easy Instance Difficult Difficult Instance Instance Ripup and Ripup and Reroute Reroute Fast Fast Slow Slow Recursion tree Recursion tree traversal order traversal order Graph Graph-

• based

based Medium Medium Medium Medium Missing Missing candidates candidates candidates candidates Congestion Congestion N ti ti N ti ti Sl Sl F t F t Penalty Penalty Negotiation Negotiation (Pathfinder) (Pathfinder) Slow Slow Faster Faster Penalty Penalty increment increment

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Negotiated Congestion Router Negotiated Congestion Router g g g g without GR without GR

Advantages Advantages

N l it bl N l it bl No granularity problem No granularity problem

Disadvantages Disadvantages Disadvantages Disadvantages

Doesn't scale well Doesn't scale well Impractical for large problems Impractical for large problems

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Age of global ro ting Age of global ro ting Age of global routing Age of global routing

Today problems involve many millions of Today problems involve many millions of gates gates gates gates

Time to market and productivity important Time to market and productivity important p y p p y p

The age of global routing

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Global ro ting applications Global ro ting applications Global routing applications Global routing applications

Full chip Full chip S b hi bl k l l S b hi bl k l l Subchip or block level Subchip or block level Specialty Specialty Specialty Specialty

Analog Analog

Symmetry Symmetry Length constraints Length constraints g

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Design Methodologies Design Methodologies Design Methodologies Design Methodologies

• Fixed die

Fixed die V i bl di V i bl di

• Variable die

Variable die

• Constrained die

Constrained die

• Constrained die

Constrained die

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Fi ed Die Methodolog Fi ed Die Methodolog Fixed Die Methodology Fixed Die Methodology

Dominates industry and academia Dominates industry and academia f Placement consists of two stages: Placement consists of two stages:

Coarse Coarse Coarse Coarse Detail Detail

Global routing Global routing

Timing / Congestion Driven Timing / Congestion Driven Timing / Congestion Driven Timing / Congestion Driven

Detail routing Detail routing

Multilevel to increase capacity and fix problems Multilevel to increase capacity and fix problems due to abstraction due to abstraction

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due to abstraction due to abstraction

Pre io s Work Pre io s Work Previous Work Previous Work

• Multicommodity Flow Albrecht C (2001)

Multicommodity Flow Albrecht C (2001) B R Ch M d P D (2006) B R Ch M d P D (2006)

• BoxRouter Cho M. and Pan D., (2006)

BoxRouter Cho M. and Pan D., (2006)

• Lagrange Relaxation Roy J and Markov I

Lagrange Relaxation Roy J and Markov I

• Lagrange Relaxation Roy J, and Markov I

Lagrange Relaxation Roy J, and Markov I (2007) (2007)

• FastRoute Pan M. and Chu C. (2007)

FastRoute Pan M. and Chu C. (2007) Ri h lit t T t ti Ri h lit t T t ti

• Rich literature. Too many to mention

Rich literature. Too many to mention

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Bin Based Bin Based Bin Based Bin Based

Each region becomes a node in the graph Each region becomes a node in the graph Adjacent regions form edges in the graph Graph may be 2D or 3D

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Global Ro ting Iss es Global Ro ting Iss es Global Routing Issues Global Routing Issues

Bin Model Granularity Errors Bin Model Granularity Errors Extending the Domain of Global Routing Extending the Domain of Global Routing

Placement Placement Placement Placement Detail Routing Detail Routing

Methodology issues Methodology issues

Variable Die Variable Die Variable Die Variable Die Constrained Die Constrained Die

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Gran larit Errors Gran larit Errors Granularity Errors Granularity Errors

Bin model counts edge

Bin model counts edge Bin model counts edge Bin model counts edge crossings crossings

Bin model fails to capture in

Bin model fails to capture in- Bin model fails to capture in Bin model fails to capture in bin density bin density

Bin size 15

Bin size 15-50 tracks 50 tracks s e 5 s e 5 50 ac s 50 ac s typically typically

ISPD benchmark contest 30

ISPD benchmark contest 30-

• 50 tracks

50 tracks

Effect prominent in better

Effect prominent in better p placements placements

Obvious during detail routing

Obvious during detail routing g g g g

Wire widths not taken into

Wire widths not taken into account account

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Why bin boundary Why bin boundary y y y y approximation? approximation?

Pin locations are known Pin locations are known E i h i h i l E i h i h i l Exact is easy enough with interval trees Exact is easy enough with interval trees Non Non-uniform wire pitches (3D case) uniform wire pitches (3D case) Non Non-uniform wire pitches (3D case) uniform wire pitches (3D case) Use layer direction orthogonality Use layer direction orthogonality y g y y g y

Layers either horizontal or vertical Layers either horizontal or vertical

O(l N) ti l it O(l N) ti l it O(logN) time complexity O(logN) time complexity

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Global router should do Global router should do placement placement

• Half

Half-

• perimeter wire length is replaced with

perimeter wire length is replaced with Steiner trees Steiner trees Steiner trees Steiner trees

Far more accurate wire length Far more accurate wire length

• Accurate density calculations

Accurate density calculations

Detail routing possible if Detail routing possible if

B b k

s d

b b

∈ ∀ + ≤ ,

g p g p

• Why not detail placement?

Why not detail placement?

s d

b b

,

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Congestion a poor metric Congestion a poor metric Congestion: a poor metric Congestion: a poor metric

Cost = wirelength + congestion + timing

Cost = wirelength + congestion + timing

Cost = wirelength + congestion + timing

Cost = wirelength + congestion + timing P P W C

c c t t w

β β β + + =

c t w

β β β

∑ =

= N n

n W W

1

) (

∑ =

= N p p D p

Pt

1

( )

t l C R f D

g p

, , , =

( )

B

F il di i l i

( )

∑ =

= B b c c

b P P

1

Fails dimension analysis Reliance on benchmarks for tuning

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Reliance on benchmarks for tuning

Timing Penalt Re isited Timing Penalt Re isited Timing Penalty Revisited Timing Penalty Revisited

Rewrite timing penalty in terms of net length

Rewrite timing penalty in terms of net length

( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )

p lowerBound p length p length p lowerBound p upperBound p length p upperBound p length P { < > −

( ) ( ) ( ) ( )

• therwise

p lowerBound p length p length p lowerBound Pt

{

< − =

( )

∑ = W p length

where

( )

∑ =

∈ ∀ p n n

W p length

Successfully used on many microprocessor designs

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What abo t Congestion? What abo t Congestion? What about Congestion? What about Congestion?

Detour length replaces congestion term

Detour length replaces congestion term How far to travel to get to uncongested area How far to travel to get to uncongested area

How far to travel to get to uncongested area

How far to travel to get to uncongested area

Timing and congestion rewritten in terms of

Timing and congestion rewritten in terms of g g g g length length

All terms in cost function are length

All terms in cost function are length based based

All terms in cost function are length

All terms in cost function are length-based based

Scales properly

Scales properly

Tradeoffs between terms straightforward

Tradeoffs between terms straightforward

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Calculating Detour Length Calculating Detour Length Calculating Detour Length Calculating Detour Length

• During placement, use congestion map to detour length

During placement, use congestion map to detour length

• algorithm. Kangh and Xu (2003)
• algorithm. Kangh and Xu (2003)
• But during global routing, we have all the information to

But during global routing, we have all the information to directly compute it. directly compute it.

• Possible metrics

Possible metrics

• How far are we outside the bounding box of a net’s pins

How far are we outside the bounding box of a net’s pins

• Excess wire length above minimum Steiner tree bound

Excess wire length above minimum Steiner tree bound

• Net segment detour length

Net segment detour length

• Use traditional congestion metric as a tie breaker.

Use traditional congestion metric as a tie breaker. g

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Global router should do detail Global router should do detail routing routing

• Alignment of orthogonal resources within

Alignment of orthogonal resources within the bin or region the bin or region the bin or region the bin or region

• Known as virtual pin resources or feedthru

Known as virtual pin resources or feedthru Known as virtual pin resources or feedthru Known as virtual pin resources or feedthru assignment assignment

• Long range planning

Long range planning

• Minimize vertical constraint cycles

Minimize vertical constraint cycles

• Minimize vertical constraint cycles

Minimize vertical constraint cycles

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Minimi ing Vertical Constraints Minimi ing Vertical Constraints Minimizing Vertical Constraints Minimizing Vertical Constraints

Forces new column

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Minimi ing Vertical Constraints Minimi ing Vertical Constraints Minimizing Vertical Constraints Minimizing Vertical Constraints

A B A B C C A B B C A A B C A B C C B C A B

Most detail routing fails at the pins Detail router appreciates help from the global router pp p g

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Minimizing Vertical Constraint Minimizing Vertical Constraint g Cycles Cycles

Ways to break cycle Ways to break cycle

M i t l i i t M i t l i i t Move virtual pin assignment Move virtual pin assignment Swap equivalent pins of a gate (rewrite netlist) Swap equivalent pins of a gate (rewrite netlist) p q p g ( ) p q p g ( ) Rotate a cell Rotate a cell M ll M ll Move a cell Move a cell

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Track assignment Track assignment Track assignment Track assignment

• 1D routing

1D routing C lk C lk

• Crosstalk

Crosstalk

• Noise

Noise

• Noise

Noise

• Early channel

Early channel-

• based detail routers (Greedy,

based detail routers (Greedy, y ( y ( y Mighty) Mighty) S l i li i t titi i S l i li i t titi i

• Solve using linear assignment, partitioning,

Solve using linear assignment, partitioning, linear programming... linear programming... p g g p g g

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Sim ltaneo s Ro ting Sim ltaneo s Ro ting Simultaneous Routing Simultaneous Routing

• Power, clock, signal routed simultaneously

Power, clock, signal routed simultaneously

Wid i i l i Wid i i l i

Wide wire requires planning

Wide wire requires planning

Verified Saxena and Gupta (2003)

Verified Saxena and Gupta (2003) p ( ) p ( )

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S nthesis d ring global ro ting S nthesis d ring global ro ting Synthesis during global routing Synthesis during global routing

• Buffer synthesis

Buffer synthesis G i i G i i

• Gate resizing

Gate resizing

• Scan chain synthesis

Scan chain synthesis

• Scan chain synthesis

Scan chain synthesis

• Clock tree synthesis

Clock tree synthesis y

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Other design methodologies Other design methodologies Other design methodologies Other design methodologies

• Variable die

Variable die C i d di C i d di

• Constrained die

Constrained die

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Variable Die Variable Die Variable Die Variable Die

White space is manipulated to insure no overflow Placement is not fixed. Relative placement may change as well

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Variable Die Variable Die Variable Die Variable Die

• Applicable to block level

Applicable to block level E l f hi l l E l f hi l l

• Early stages of chip level

Early stages of chip level

• Minimize area

Minimize area

• Minimize area

Minimize area

• Trade off # of routing layers versus cost

Trade off # of routing layers versus cost g y g y

• Guarantees completion

Guarantees completion

• Minimizes congestion (controversial)

Minimizes congestion (controversial)

• Original P&R algorithm using channels

Original P&R algorithm using channels

• Original P&R algorithm using channels

Original P&R algorithm using channels

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Variable Die Algorithm Variable Die Algorithm Variable Die Algorithm Variable Die Algorithm

Virtual pin assignment determines Virtual pin assignment determines

• rthogonal (vertical) resources
• rthogonal (vertical) resources
• rthogonal (vertical) resources
• rthogonal (vertical) resources

Partition into virtual regions to determine Partition into virtual regions to determine Partition into virtual regions to determine Partition into virtual regions to determine horizontal resources horizontal resources If all pins at center of standard cell If all pins at center of standard cell

Perfect decomposition Perfect decomposition Perfect decomposition Perfect decomposition Global router decouples virtual regions Global router decouples virtual regions Perfect parallelism Perfect parallelism – – all core regions at once. all core regions at once. Blocks/macros complicate things Blocks/macros complicate things

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Blocks/macros complicate things Blocks/macros complicate things

Macro Regions Macro Regions Macro Regions Macro Regions

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Inp t to Global Ro ter Inp t to Global Ro ter Input to Global Router Input to Global Router

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Region Definition Region Definition Region Definition Region Definition

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O tp t of Global Ro ter O tp t of Global Ro ter Output of Global Router Output of Global Router

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Chip Design Chip Design Chip Design Chip Design

Chip design process uses iterative Chip design process uses iterative refinement not one refinement not one shot shot refinement not one refinement not one-shot shot Design space exploration at beginning Design space exploration at beginning Design space exploration at beginning Design space exploration at beginning

What is possible? What is possible?

As knowledge is acquired, more and more As knowledge is acquired, more and more aspects become fixed aspects become fixed aspects become fixed aspects become fixed

Die size become fixed Die size become fixed I/Os become fixed I/Os become fixed

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Constrained Die Constrained Die Constrained Die Constrained Die

Designer cares only about interface of block Designer cares only about interface of block

• r chip remain constant during iterations
• r chip remain constant during iterations
• r chip remain constant during iterations
• r chip remain constant during iterations

Footprint important Footprint important p p p p Physical location of internals irrelevant Physical location of internals irrelevant

Propose Constrained Die Methodology Propose Constrained Die Methodology Propose Constrained Die Methodology Propose Constrained Die Methodology

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Constrained Die Constrained Die Constrained Die Constrained Die

Constrained die compaction graph in y direction Constrained die compaction graph in y direction. Dotted line shows constrained die fixed edge.

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Compacting global ro ter Compacting global ro ter Compacting global router Compacting global router

• Global router compacts virtual regions such that block/chip

Global router compacts virtual regions such that block/chip constraints maintained. constraints maintained.

• Maximize degrees of freedom

Maximize degrees of freedom

• Delay whitespace allocation as much as possible

Delay whitespace allocation as much as possible

• Delay whitespace allocation as much as possible

Delay whitespace allocation as much as possible

• Guarantee solution

Guarantee solution T d ff h i T d ff h i

• Trade offs much easier

Trade offs much easier

• ECO compatible

ECO compatible

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Variable Die Algorithm Variable Die Algorithm g Problems Problems

Detail routing slow if not in parallel Detail routing slow if not in parallel C i i d b b C i i d b b Compaction is done by maze router because Compaction is done by maze router because topology changes topology changes Global router errors Global router errors Estimate off by 1 track Estimate off by 1 track Estimate off by 1 track Estimate off by 1 track Assignments to wrong region Assignments to wrong region Solved by Multilevel but this negates parallelism Solved by Multilevel but this negates parallelism C li t d C li t d Complicated Complicated

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Itools Global Routing Algorithm Itools Global Routing Algorithm

globe(void) { globe(void) { setup_routing_regions() ; setup_routing_regions() ; create prerouting() ; create prerouting() ; create_prerouting() ; create_prerouting() ; instantiate_power_ground_networks() ; instantiate_power_ground_networks() ; process_scan_chains() ; process_scan_chains() ; process clocktrees() ; process clocktrees() ; process_clocktrees() ; process_clocktrees() ; steiner() ; steiner() ; initialize_gr_cost() ; initialize_gr_cost() ; switchable segment opt() ; switchable segment opt() ; switchable_segment_opt() ; switchable_segment_opt() ; area_minimization() ; area_minimization() ; freeway_assign() ; freeway_assign() ; f d h i () f d h i () feedthru_assign() ; feedthru_assign() ; for( c = 1 ;c <= reassign_limitG ; c++){ for( c = 1 ;c <= reassign_limitG ; c++){ cell_swap_opt() ; cell_swap_opt() ; detour_minimization() detour_minimization() ; } /* end for( loop_cnt = 1... */ } /* end for( loop_cnt = 1... */ switchable segment opt() ; switchable segment opt() ; _ g _ p () ; _ g _ p () ; area_minimization() ; area_minimization() ; congestion_minimization() ; congestion_minimization() ; vertical constraint min() ; vertical constraint min() ; vertical_constraint_min() ; vertical_constraint_min() ; }

Area Minimization Area Minimization

void area_minimization(GRAPHPTR region_graph,const int MLIMIT) { f ( t 1 t < G t++ ){ for( count=1; count <= area_passesG; count++ ){ // Compact & find longest path but don't move cells. compact_fixed_area() ; // Determine set of regions where area opt is warranted // Determine set of regions where area opt is warranted. xpaths = find_M_longestPath(region_graph,ICCOMPACT_X,MLIMIT) ; xcritical = assign_critical_regions( xpaths, ICCOMPACT_X ) ; ypaths = find_M_longestPath(region_graph,ICCOMPACT_Y,MLIMIT) ; yp _ _ g ( g _g p _ ) ycritical = assign_critical_regions( ypaths, ICCOMPACT_Y ) ; // Reroute paths on the critical path. for( p = 1 ; p <= xcritical.num ; p++ ){ th iti l th [ ] path_p = xcritical.paths[p] ; reroute_critical_nets(path_p,ICCOMPACT_X) ; } for( q = 1 ; q <= ycritical num; q++ ){ for( q = 1 ; q <= ycritical.num; q++ ){ path_p = ycritical.paths[q] ; reroute_critical_nets(path_p,ICCOMPACT_Y) ; } } /* end for( count=1; count <= area_passeS... */ // Move the cells and rebuild the tile database and graph. compact_variable_area() ; } /* () */

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} /* end area_minimization() */

Deto r Minimi ation Deto r Minimi ation Detour Minimization Detour Minimization

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Detour Minimization Detour Minimization Detour Minimization Detour Minimization

void detour_minimization(void) {

• bstacles = build_feed_obstacles() ;

for( row = 1 ; row <= numRowsG ; row++ ){ comb_a_row(row,obstacles) ; } free_feed_obstacles() ; } /* end detour_minimization() */ void comb_a_row(int row,TILEPLANEPTR obstacles) { // A detour is a C or inverted C. d t fi d t f d t ( ) detours = find_set_of_detours(row) ; // Remove net segments containing the detour // making the virtual pin now unused. remove detour feeds(detours) ; remove_detour_feeds(detours) ; // Determine the set of unused virtual pin locations. feeds = unused_feeds(row,obstacles) ; // Use linear assignment to assign detour // Use linear assignment to assign detour // segment to virtual pins. new_cost = reassign_feeds(row,detours,feeds) ; } /* end comb a row() */

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} / end comb_a_row() /

S mmar S mmar Summary Summary

• Global routers should do detail placement

Global routers should do detail placement

• Global routers should aid detail routers

Global routers should aid detail routers Global routers should aid detail routers Global routers should aid detail routers Minimize cycles in constraint graphs Minimize cycles in constraint graphs L li t ti l t i t L li t ti l t i t Long range alignment vertical constraints Long range alignment vertical constraints

• Simultaneous routing of signals, power and clocks

Simultaneous routing of signals, power and clocks

• Variable die and constrained die methodologies to

Variable die and constrained die methodologies to remove congestion remove congestion remove congestion remove congestion

• Integral component to floorplanning

Integral component to floorplanning

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