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PAM : A P rocessor A geing M odel Based on Critical Path Delays Negar Miralaei, Jyothish Soman, Timothy Jones March 2014 Designing with Uncertainty - Opportunities & Challenges Workshop Agenda Ageing model to Application characterise

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SLIDE 1

PAM: A Processor Ageing Model

Based on Critical Path Delays

Negar Miralaei,

Jyothish Soman, Timothy Jones

March 2014 Designing with Uncertainty - Opportunities & Challenges Workshop

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SLIDE 2

Agenda

  • Ageing model to

characterise the applications’ behaviour

  • Micro-Architectural

model

  • Runtime based ageing

prevention schemes

2

Application Multicore/ Many-core Ageing Prevention

Ageing Model

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SLIDE 3

Transistor Ageing

  • Major Failure Mechanisms

3

Drain(D) Source(S) Gate Oxide p/n-well (p/n)

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SLIDE 4

Transistor Ageing

4

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SLIDE 5

The Gaps in Knowledge

  • Single core vs multicore and many-core
  • Memory and cache vs processor
  • All the units within the processor
  • The level of implementation

5

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SLIDE 6

Critical Path Delay Estimation

6

  • An ageing model based on critical path delay variations
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SLIDE 7

Critical Path Delay Estimation

Logic

(Full Adder)

Memory

(SRAM cell)

Delay of FO4

7

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SLIDE 8

PAM: a Processor Ageing Model

8

Gem5

Failure Mechanisms: NBTI & HCI Calculate the access time

Calculate the switching delay for each structural unit

  • Process variation

parameters

  • Floorplan file
  • Frequency
  • Source voltage
  • Temperature
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SLIDE 9

Simulation Environment

  • Technology parameters
  • Process technology = 32nm
  • Vdd = 1.0 V
  • Frequency = 2.0 GHz
  • Single out of Order ARM v7 core
  • Ageing Parameters
  • Temperature = 80oC
  • Vth0 = 200mV
  • Oxide thickness = 0.65 nm
  • Effective gate length = 17nm
  • Gem5 Simulator
  • SPECCPU 2000 Benchmarks
  • VARIUS Framework

9

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SLIDE 10

Results

Structural Units Delay (ps)

Different structural units delays for one benchmark, ran for 1 billion instructions

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SLIDE 11

Results

Architectural Registers delay within Renaming Unit for all SPEC2000 benchmarks, ran for 1 billion instructions

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SLIDE 12

Results

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Comparison of the maximum critical path delays for 10 different initial variations, ran for SPEC2000 benchmarks and for 1 billion instructions

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SLIDE 13

Summary

  • Micro-Architectural ageing

model

  • Online mechanism giving

state of processor’s age

  • Characterising the ageing

due to applications’ behaviour

13

Application Multicore/ Many-core Ageing Prevention

PAM

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SLIDE 14

Future Work

  • Transistor level model
  • Add more failure mechanisms (EM, TDDB, RTN, etc.)
  • Combat processor ageing
  • Compiler techniques (JIT environment)
  • Scheduling
  • DVFS
  • Code restructuring and algorithm selection
  • Create a heterogeneous CMP with “hot spares”

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SLIDE 15

Thank you

Questions Please?

negar.miralaei@cl.cam.ac.uk http://www.cl.cam.ac.uk/~nm537/ Project webpage: http://www.cl.cam.ac.uk/research/comparch/research/dome.html