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Overview of the ARM architecture Simon Aittamaa Dept. of Computer Science, Electrical and Space Engineering Lule University of Technology October 08, 2012 1 / 36 1. Introduction 1.1. Architecture 1.2. Registers 1.3. Instruction Set 1.4.

SLIDE 1

Overview of the ARM architecture

Simon Aittamaa

Dept. of Computer Science, Electrical and Space Engineering

Luleå University of Technology

October 08, 2012

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SLIDE 2

1. Introduction

1.1. Architecture 1.2. Registers 1.3. Instruction Set 1.4. System Bus 1.5. Pipeline

2. Examples

2.1. Pipeline 2.2. Conditional Instructions 2.3. Expressive Syntax 2.4. Context Save/Restore

3. Closing Thoughts

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SLIDE 3

1. Introduction

1.1. Architecture 1.2. Registers 1.3. Instruction Set 1.4. System Bus 1.5. Pipeline

2. Examples

2.1. Pipeline 2.2. Conditional Instructions 2.3. Expressive Syntax 2.4. Context Save/Restore

3. Closing Thoughts

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SLIDE 4

Introduction

Why ARM? The most common 32-bit platform (in numbers produced) In 2010 ≈ 95% of the smartphone market (low-power design) Windows 8, estimates point to ARM on ≈ 23% of all PCs by 2015 Similar to MIPS, yet different. . . What is ARM? “Acorn RISC Machine” (1983-1989) “Advanced RISC Machines” – ARM Holdings (1990-present)

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SLIDE 5

Introduction

ARM Holdings License their technology to others. . . Currently licenced by Intel, Samsung, Texas Instruments, Analog Devices, Atmel, Freescale, Nvidia, Qualcomm, STMicroelectronics and Renesas

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SLIDE 6

Architecture

Which architecture? Architecture Family ARMv1 ARM1 ARMv2 ARM2, ARM3 ARMv3 ARM6, ARM7 ARMv4 StrongARM, ARM7TDMI, ARM9TDMI ARMv5 ARM7EJ, ARM9E, ARM10E, XScale ARMv6 ARM11, Cortex-M ARMv7 Cortex-A, Cortex-M, Cortex-R ARMv8 N/A

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SLIDE 7

Architecture

Which architecture? Architecture Family ARMv1 ARM1 ARMv2 ARM2, ARM3 ARMv3 ARM6, ARM7 ARMv4 StrongARM, ARM7TDMI, ARM9TDMI ARMv5 ARM7EJ, ARM9E, ARM10E, XScale ARMv6 ARM11, Cortex-M ARMv7 Cortex-A, Cortex-M, Cortex-R ARMv8 N/A

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SLIDE 8

Architecture

Features Load/Store architecture 16-bit or 32-bit instructions Conditional execution of instructions (only for 32-bit instructions) “Mostly” single-cycle execution of instructions 2-level interrupt priority (irq and fiq) Extended by the manufacturer VIC (Philips) or AIC (Atmel). . . 6 processor-modes. . . user, sys, svc, irq, fiq, und, and abt

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SLIDE 9

Registers

16 registers (32-bit) General-purpose registers: r0-r12 Stack-register: r13 Link-register: r14 Depending on processor mode, some registers are “shadowed”. . . Current Program Status Register (CPSR) N, Z, C, and V flags Interrupt enable bits (irq, fiq) Processor mode (sys, svc, und, etc.) Saved in SPSR_xxx register on interrupt entry

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SLIDE 10

Registers

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SLIDE 11

Registers

16 registers (32-bit) General-purpose registers: r0-r12 Stack-register: r13 Link-register: r14 Depending on processor mode, some registers are “shadowed”. . . Current Program Status Register (CPSR) N, Z, C, and V flags Interrupt enable bits (irq, fiq) Processor mode (sys, svc, und, etc.) Saved in SPSR_xxx register on interrupt entry

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SLIDE 12

Registers

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SLIDE 13

Instruction Set

ARM Fixed 32-bit length All registers accessible Thumb Fixed 16-bit length Lower registers accessible (r0-r7) Subset of instruction-set available

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SLIDE 14

Instruction Set

Data processing instructions (1 cycle) mov r0, r1 add r0, r1, r2 Data processing instructions (3 cycles) bl label (24-bit offset +/- 32MB) r14 (lr) becomes PC+8 when linking mov lr, pc mov pc, r0 bx r0

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SLIDE 15

Instruction Set

Data store instruction (2 cycles) str r0, [r1] stmia r13!, {r0-r7,lr} (3 + n cycles, where n is number of registers) Data load instruction (3 cycles) ldr r0, [r1] or ldr r0, =0xdeadbeef ldr r15, =memset (when r15 is destination, 5 cycles) ldmdb r13!, {r0-r7,pc} (4 + n cycles, where n is number of registers) Alignment of data Requires correct alignment for 16-bit and 32-bit loads.

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SLIDE 16

Instruction Set

Software interrupt svc #0x102 ARM 24-bit immediate field Thumb 8-bit immediate field svc-mode (r14 is PC+4) Modifying CPSR and SPSR mrs r0, CPSR (r0 ← CPSR) msr r0, SPSR (r0 → CPSR) msr r0, CPSR_f (_f indicates only N, Z, C, and V) Complete access only allowed in priviliged mode (!user)

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SLIDE 17

Instruction Set

Co-Processor instructions Allows for extending of instruction-set by co-processors, could also be emulated using und-mode. stc cp0, cr0, [r0] (store from address [r0] to register cr0 of cp0) cdp cp0, op, cr0, cr1 (perform op of cp0 on cr0 and cr1) mrc cp0, op, r0, cr0, cr1 (perform op of cp0 on cr0 and cr1 and store in r0)

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SLIDE 18

Instruction Set

Binary encoding of instruction ARM has 19 “schemes” or “types” MIPS has 3 “schemes” or “types”

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SLIDE 19

System Bus

AMBA (Advanced Microcontroller Bus Architecture ASB (Advanced System Bus) Advanced interface (not trivial to implement) Suitable for system modules (on-chip RAM etc.) Burst-mode data transfers (DMA!) APB (Advanced Peripheral Bus) Simpler and slower (usually half the speed of ASB) Is actually a slave of ASB Mainly for peripheral devices: UART, Timers, USB, etc.

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SLIDE 20

Pipeline

3-stage pipeline Fetch, decode, and execute No branch/load delay slots, pipeline is stalled or utilized Simple, no register forwarding etc.

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SLIDE 21

1. Introduction

1.1. Architecture 1.2. Registers 1.3. Instruction Set 1.4. System Bus 1.5. Pipeline

2. Examples

2.1. Pipeline 2.2. Conditional Instructions 2.3. Expressive Syntax 2.4. Context Save/Restore

3. Closing Thoughts

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SLIDE 22

Pipeline

Pipeline overview

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SLIDE 23

Pipeline

Pipeline flow

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SLIDE 24

Pipeline

Data processing instruction (pipeline)

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SLIDE 25

Pipeline

Data store instruction (flow)

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SLIDE 26

Pipeline

Data store instruction (pipeline)

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SLIDE 27

Pipeline

Data store instruction (pipeline)

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SLIDE 28

Conditional Instructions

If-statement

i f ( r0 == r1 ) r2 = r3 [ 0 ] ; else r2 = r3 [ 1 ] ;

If-statement

cmp r0 , r1 ldreq r2 , [ r3 ] ldrne r2 , [ r3 , #4] 28 / 36

SLIDE 29

Expressive Syntax

C-code

i f ( r2 < TBL_SIZE ) { r1 [ r2 ∗ 4 ] ( ) ; } return ;

ARM-code

cmp r2 , TBL_SIZE l d r l t r0 , [ r1 , r2 , l s l #2] movlt l r , pc movlt pc , r0 ldmfd r13 ! , { r4−r7 , pc }^ 29 / 36

SLIDE 30

Context Save/Restore

MIPS: Context save

/ / Save user regs . subu $29 , $29 , 116 sw $1 , 0($29 ) . . . sw $31 , 108($29 ) / / Save return address mfc0 $26 , $14 nop sw $26 , 112($29 ) / / Save sp la $1 , t t _ c u r r e n t lw $1 , 0($1 ) nop sw $29 , 0($1 ) nop

MIPS: Context restore

/ / Load sp la $29 , t t _ c u r r e n t lw $29 , 0($29 ) nop lw $29 , 0($29 ) nop / / Restore user regs lw $1 , 0($29 ) . . . lw $31 , 108($29 ) / / Restore return addr lw $26 , 112($29 ) addu $29 , $29 , 116 / / Return from i n t e r r u p t j r $26 rfe 30 / 36

SLIDE 31

Context Save/Restore

ARM: Context save

/ / Get user mode sp stmfd sp ! , { r0 } stmdb sp , { sp }^ nop ldmdb sp , { r0 } / / Store return address sub l r , l r , #4 stmfd r0 ! , { l r } / / Start using l r mov l r , r0 ldmfd sp ! , { r0 } / / Save user mode regs stmfd l r , { r0−r14 }^ nop sub l r , l r , #60 / / Save SPSR. mrs r0 , SPSR stmfd l r ! , { r0 } / / Save stack pointer l d r r0 , = t t _ c u r r e n t l d r r0 , [ r0 ] s t r l r , [ r0 ]

ARM: Context restore

/ / Load sp l d r r0 , = t t _ c u r r e n t l d r r0 , [ r0 ] l d r l r , [ r0 ] / / Restore SPSR ldmfd l r ! , { r0 } msr r0 , SPSR / / Restore user mode regs ldmfd l r , { r0 , r14 } nop add l r , l r , #60 / / Return from i n t e r r u p t ldmfd l r , { pc }^ 31 / 36

SLIDE 32

1. Introduction

1.1. Architecture 1.2. Registers 1.3. Instruction Set 1.4. System Bus 1.5. Pipeline

2. Examples

2.1. Pipeline 2.2. Conditional Instructions 2.3. Expressive Syntax 2.4. Context Save/Restore

3. Closing Thoughts

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SLIDE 33

Closing Thoughts

ARM and processor modes. . . Can be a daunting (to say the least) task to grasp Linux/eCos/FreeRTOS to the rescue (ignorance is bliss?) Buckle down and read the reference manual! (It was hard for me, it should be hard for you!) Cortex-M[0,1,3,4]? Cortex-M[0,1,3,4] Thumb2 instruction-set and a very powerful interrupt controller (standard across all Cortex-M[0,1,3,4] processors). Forget processor modes, shadowed registers (ok, there is one), it’s ARM done right! What about 64-bit? MIPS became 64-bit around -99. . . ARMv8 (arrived late 2011) will support 64-bit but there is no implementation yet!

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SLIDE 34

Closing Thoughts

Lecture this Wednesday Laboration 4: “The C-lab” Slides will be updated. . . Brief introduction to C The most common mistakes (≈ 50% of you will make them)

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SLIDE 35

Closing Thoughts

Lecture this Wednesday Laboration 4: “The C-lab” Slides will be updated. . . Brief introduction to C The most common mistakes (≈ 50% of you will make them) Yes, you will make them even if I tell you about them. . .

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SLIDE 36

Closing Thoughts

Lecture this Wednesday Laboration 4: “The C-lab” Slides will be updated. . . Brief introduction to C The most common mistakes (≈ 50% of you will make them) Yes, you will make them even if I tell you about them. . .

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