of Chip Design 13 th September - D&R IPSoC 2018, Shanghai Samir - - PowerPoint PPT Presentation

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of Chip Design 13 th September - D&R IPSoC 2018, Shanghai Samir - - PowerPoint PPT Presentation

The Changing Techonomics of Chip Design 13 th September - D&R IPSoC 2018, Shanghai Samir Patel - CEO Sankalp Semiconductor Industry Trends Se Semic iconductor Units its Vrs Revenue 1200 Industry to find newer 1000 efficiency models


slide-1
SLIDE 1

The Changing Techonomics

  • f Chip Design

13th September - D&R IPSoC 2018, Shanghai

Samir Patel - CEO Sankalp Semiconductor

slide-2
SLIDE 2

Industry Trends

Industry to find newer efficiency models

  • Do more with less
  • Address Just-in-Time

needs

200 400 600 800 1000 1200 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Se Semic iconductor Units its Vrs Revenue

Billions of Units Revenue ($) Billions

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SLIDE 3

Source: ARM, SMIC internal studies

SMIC SMIC SMIC SMIC SMIC SMIC SMIC

Wide Selection of Technology & Node

Manufacturing choice explosion

Growing Number of Design Starts

  • Basic SoC design starts in the consumer segment are

expected to grow at a 19 percent CAGR

  • Industrial IoT ASIC design starts are projected to grow

by 25 percent through 2021 Source: Semico report

slide-4
SLIDE 4

ASoC Explosion

I2C

ASOC

Wireless Communication Special IP

DSP HW Accelerators Security

Sensor / Actuator Interface

ADC GPIO DAC 13C SPI SD PWM

App SW

Control Systems Human interface Automotive Medical

CPU / DSP Protocols LWM2M CoAP

slide-5
SLIDE 5

Market Drivers

  • Variety explosion
  • IoT, AI, Cloud & 5G
  • Just-in-Time demand
  • Huge increase in demand in China

Market Drivers & Industry Response

Industry response

  • Preference for building System
  • n Chip (SoC)
  • Emphasis on REUSE
  • Contract Design
slide-6
SLIDE 6

ASoC Companies

  • Derivatives – Size reduction, product line

management, features enhancement

  • IP & IP Customization Services– Porting

to newer technologies nodes

Systems Companies

  • End-to-End Chip Design
  • Enabling through out the chip ecosystem
  • Test Vehicles
  • Prototyping & Fabrication

Need for Accelerated Time to Market

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SLIDE 7

SoC Implementation RTL Design & Verification IP Choice Analog & Mixed Signal Design Custom Layout and Place & Route Validation & Characterization SPEC Definition Technology Foundation & Foundry Interface

Your ASoC Realization Partner

Cooperative business models to help solve your problems

slide-8
SLIDE 8

Thank You