NAND Flash Memory Laura M. Grupp * , John D. Davis , Steven Swanson - - PowerPoint PPT Presentation

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NAND Flash Memory Laura M. Grupp * , John D. Davis , Steven Swanson - - PowerPoint PPT Presentation

Nov 12, 2023 186 likes •512 views

The Bleak Future of NAND Flash Memory Laura M. Grupp * , John D. Davis , Steven Swanson * * Non-volatile Systems Laboratory Department of Computer Science and Engineering University of California, San Diego Microsoft Research 1 Flashs

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The Bleak Future of NAND Flash Memory

Laura M. Grupp*, John D. Davis , Steven Swanson*

*Non-volatile Systems Laboratory

Department of Computer Science and Engineering University of California, San Diego

Microsoft Research

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Flash’s Future: Bright

Reliability Performance Cost Per Capacity

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Performance Cost Per Capacity

Flash’s Future: Bright Bleak

 Decreasing Write Budget Increasing Density 

Reliability

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4 1000 2000 3000 4000 5000 6000 7000 8000 Low Density Flash Disk Drives Write Latency (µs)

Cost Per Capacity

 Decreasing Write Budget Increasing Density 

Reliability

Flash’s Future: Bright Bleak

Performance

Expected Performance Gap

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5 1000 2000 3000 4000 5000 6000 7000 8000 Low Density Flash Disk Drives High Density Flash Write Latency (µs)

Cost Per Capacity

 Decreasing Write Budget Increasing Density 

Reliability

Will the price decline be enough?

Flash’s Future: Bright Bleak

Performance

Expected Performance Gap

What performance & scaling trends can we expect from our SSDs?

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Predicting Future Flash-Based SSDs

Model’s Equations Fixed SSD Architecture Flash Chip Trends SSD Trends

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PCIe Link

The Constant-Die-Count SSD (SSD-CDC)

  • Represents High-End

(FusionIO, Virident, OCZ)

  • Baseline

– 96 dies – 320 GB – 34nm, MLC

  • Assumptions

– Constant die count – Unlimited PCIe Link – Channel Speed: 400MB/s

Flash Die 0 Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 0 Flash Die 1 Flash Die 2 Flash Die 3

Channel 23 Channel 0

. . . . . . . . .

Controller

Flash Die 0 Flash Die 1 Flash Die 2 Flash Die 3

Channel 1

. . .

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The Metrics

  • Capacity
  • Latency
  • Throughput
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Increasing Density: Multi-bit Cells

SLC Single-Level Cell (1 bit) MLC Multi-Level Cell (2 bits) TLC Triple-Level Cell (3 bits) Floating Gate (modifies VTH) “0” “1” “00” “01” “10” “11” VTH Range VTH Range VTH Range

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10 5 10 15 20 25 30 35 40 2009 2014 2019 2024 Feature Size (nm) Year ITRS Technology Trend Target Time

Increasing Density: Moore’s Law

25nm-34nm 6.5nm

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16 64 256 1024 4096 16384 20 40 60 80 100 SSD Capacity (GB) Feature Size (nm) TLC-3 MLC-2 SLC-1

Capacity

43x SSD-CDC Best Possible by 2024

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The Metrics

  • Capacity: 43x
  • Latency
  • Throughput
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Collecting Flash Latency Trends

  • In-house flash testing rig
  • XUP Virtex-II
  • Daughter board
  • 10ns resolution
  • Chip Collection
  • 45 chips
  • 6 companies
  • 25nm-72nm
  • SLC, MLC, TLC
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Empirical Data

0.0 1.0 2.0 3.0 8 32 128 512 Chip Write Latency (ms) Feature Size (nm) TLC-3 MLC-2 SLC-1

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0.0 1.0 2.0 3.0 8 32 128 512 Chip Write Latency (ms) Feature Size (nm) SLC-1 MLC-2 TLC-3

Scaling Trends in Empirical Data

2x 2x

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0.0 1.0 2.0 3.0 16 64 256 1024 4096 16384 SSD-CDC Write Latency (ms) SSD Capacity (GB) TLC-3 MLC-2 SLC-1

Write Latency of SSD-CDC

2.6x

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The Metrics

  • Capacity: 43x
  • Latency: 2.6x
  • Throughput
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500 1000 1500 2000 2500 3000 3500 16 64 256 1024 4096 16384 SSD-CDC Write Bandwidth (MB/s) SSD Capacity (GB) SLC-1 MLC-2 TLC-3

Increased Page Size

MLC: 4kB, TLC 8kB

0.7x

Reduced Bandwidth

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200 400 600 800 1000 16 64 256 1024 4096 16384 SSD-CDC Write kIOPs SSD Capacity (GB) SLC-1 MLC-2 TLC-3

IOPs – 512B Random Accesses

Fastest HDD: 0.2 kIOPs Our Slowest SSD: 32.0 kIOPs 0.4x

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The Metrics

  • Capacity: 43x
  • Latency: 2.6x
  • Throughput: 0.7x, 0.4x
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Conclusion

  • Chip Scaling: A Mixed Bag

– Improved: Density and Cost – In Decline: Performance and Reliability

  • SSDs: Not always a perfect replacement for disks

– Do Get: High Capacity & High IOPs – Don’t Get: Low Cost & Low Latency

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Questions? The Bleak Future of NAND Flash Memory

Laura M. Grupp, John D. Davis , Steven Swanson

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The Model’s Equations

Metric Equation Capacity CapacityBaseline×

𝑪𝒋𝒖𝒕𝑸𝒇𝒔𝑫𝒇𝒎𝒎𝒒𝒔𝒑𝒌𝒇𝒅𝒖𝒇𝒆 𝑪𝒋𝒖𝒕𝑸𝒇𝒔𝑫𝒇𝒎𝒎𝒄𝒃𝒕𝒇𝒎𝒋𝒐𝒇

×

𝑮𝒇𝒃𝒖𝒗𝒔𝒇𝑻𝒋𝒜𝒇𝒄𝒃𝒕𝒇𝒎𝒋𝒐𝒇 𝑮𝒇𝒃𝒖𝒗𝒔𝒇𝑻𝒋𝒜𝒇𝒒𝒔𝒑𝒌𝒇𝒅𝒖𝒇𝒆 2

Latency 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 + 𝑷𝒘𝒇𝒔𝒊𝒇𝒃𝒆𝑴𝒃𝒖𝒇𝒐𝒅𝒛 Bandwidth 𝑫𝒊𝒃𝒐𝒐𝒇𝒎𝑫𝒑𝒗𝒐𝒖 × 𝒆𝒋𝒇𝒕𝑸𝒇𝒔𝑫𝒊𝒃𝒐𝒐𝒇𝒎 − 1 × 𝑸𝒃𝒉𝒇𝑻𝒋𝒜𝒇 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 , 𝑃𝑞𝑓𝑠𝑏𝑢𝑗𝑝𝑜 ≫ 𝐶𝑣𝑡 𝑇𝑞𝑓𝑓𝑒 IOPs 𝑫𝒊𝒃𝒐𝒐𝒇𝒎𝑫𝒑𝒗𝒐𝒖 × 𝒆𝒋𝒇𝒕𝑸𝒇𝒔𝑫𝒊𝒃𝒐𝒐𝒇𝒎 − 1 𝑫𝒊𝒋𝒒𝑴𝒃𝒖𝒇𝒐𝒅𝒛 , 𝑃𝑞𝑓𝑠𝑏𝑢𝑗𝑝𝑜 ≫ 𝐶𝑣𝑡 𝑇𝑞𝑓𝑓𝑒

Measured Value Baseline SSD Design Projected SSD Design Constant SSD Parameter

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Lifetime

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Error Rates

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Price

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Read Latency

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Read Bandwidth

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Read IOPS – 512B Random Access

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0.0 1.0 2.0 3.0 8 108 208 308 408 508 Chip Write Latency (ms) Feature Size (nm) SLC-1 MLC-2 TLC-3

Scaling Trends in Empirical Data

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Increasing Density: Multi-bit Cells

SLC Single Level Cell (1 bit) MLC Multi-Level Cell (2 bits) TLC Triple-Level Cell (3 bits) “MLC-1” Native Technology Number of Stored Bits Lower Price per Bit Floating Gate (modifies VTH) “0” “1” “0x” “1x” “00” “01” “10” “11” VTH Range VTH Range VTH Range VTH Range