Modeling Hardware Timing 1 Caches and Pipelines Peter Puschner - PowerPoint PPT Presentation

Modeling Hardware Timing 1 Caches and Pipelines Peter Puschner slides: P. Puschner, R. Kirner, B. Huber VU 2.0 182.101 SS 2016

Generic WCET Analysis Framework source Extraction of code Flow Facts Transformation of Compilation Flow Facts Calculation of Execution Scenarios object Exec-Time code Modeling WCET 2

Exec-Time Modeling Exec-time modeling typically done before WCET calculation in separate phases: 1. cache analysis 2. pipeline analysis 3. path analysis + WCET calculation Above phases may be also combined to improve accuracy: Example: (1)cache analysis (2) pipeline analysis + path-based WCET calculation. 3

Modeling Pipelines Instruction timing represented by reservation tables: IF ID EX M F WB IF ID EX M F WB 4

Modeling Pipelines Basic operations on reservation tables: Sequential combination of two reservation tables IF IF ID ID EX EX M M F F WB WB IF ID EX M F WB 5

Modeling Pipelines Basic operations on reservation tables: Parallel combination of two reservation tables IF IF ID ID EX EX M M F F WB WB IF ID EX M F WB 6

Modeling Caches Types of caches: • Instruction cache; • Data cache; • Unified cache (instruction + data); Cache layout: • direct mapped; • n-way set-associative cache; Replacement strategies: • LRU (SPARC), • pseudo-round robin (ColdFire MFC 5307, PPC 750/755) 7

Modeling Caches (2) Two approaches are presented: 1. Cache analysis integrated into IPET-based path analysis, resulting in the following phases: 1. pipeline analysis 2. cache analysis + path analysis + WCET calculation 2. Cache analysis as a separate phase using abstract interpretation (data-flow analysis), resulting in the following phases: 1. cache analysis 2. pipeline analysis 3. path analysis + WCET calculation 8

Direct Mapped Cache address word Line: valid bit (v), tag and data (k bytes) tag ld(k) bits ld(m) bits m lines Line 1 Line 2 w1 w2 wk v tag Line is selected ... by ld(m) address bits Line m 9

Modeling Caches with IPET here: Direct mapped instruction cache § Each basic block B i is divided into {B i.1 , B i.2 ,…,B i.ni } l-blocks (cache line blocks). § Two l-blocks can be • conflicting : they map to the same cache line and overwrite the cache content of the other • non-conflicting : they do not interfere in cache § Execution counter x i of B i is divided into x i = x i.j hit + x i.j miss , 1 ≤ j ≤ n i § ILP goal function: n N i hit hit miss miss ( x t x t ) ∑∑ ⋅ + ⋅ i . j i . j i . j i . j i 1 j 1 = = 10

Modeling Caches with IPET cache line block basic block (l-block) B 1 Ca che L ine Cac he line B asic B loc k 0 1 B 2 0 B 1 B 3 B 1.1 B 3.1 2 1 B 1 B 3 B 1.2 B 3.2 3 2 B 1 B 2 B 3 B 1.3 B 2.1 3 B 2 B 2.2 (i) CFG (ii) Ca che table [Y.T.Steven Li,S.Malik,A.Wolfe,95] 11

Modeling Caches with IPET Cache Constraints: • only one l-block B k.l maps to the same cache line (first access is miss): miss x 1 ≤ k . l • only two or more non-conflicting l-blocks map to the same cache line (first access is miss): miss miss x x 1 + ≤ k . l m . n • two or more conflicting l-blocks à use CCG 12

Modeling Caches with IPET • A CCG (cache conflict graph) is constructed for each cache line containing two or more conflicting l-blocks. • The sum of control flow going in the node must be the same as going out of the node: x p ( u . v , i . j ) p ( i . j , u . v ) ∑ ∑ = = i u , v u , v program exec . only once : p ( s , u . v ) 1 ∑ = u , v 13

Modeling Caches with IPET CFG and its corresponding CCG: s 1 c 1 B 1 0 p (s,4.1) 1 p (s,7.1) 11 c 2 B 2 0 0 p (7.1,7.1) p (4.1,4.1) 9 p (4.1,7.1) 10 c 3 B 3 91 0 B 4.1 B 7.1 1 c 5 B 5 9 p (7.1,4.1) 9 c 4 11 c 6 B 4 B 4.1 B 6 0 p (4.1,e) 1 p (7.1,e) 10 c 7 B 7.1 B 7 0 p (s,e) e 10 c 8 B 8 1 c 9 (ii) CCG B 9 these two lblocks are in conflict with (i) CFG each other (but with no other lblocks) [Y.T.Steven Li,S.Malik,A.Wolfe,95] à separate CCG for each conflict set 14

Modeling Caches with IPET • bounding the cache hit frequency x i.jhit : hit ( ) ( ) ( ) p i . j , i . j x p s , i . j p i . j , i . j ≤ ≤ + i . j if an l-block B i,j has only a local lifetime ( ( ) ( ) ) ExistsEdge s , i . j ExistsEdge i . j , e ¬ ∧ above constraints can be simplified as: x hit ( ) p i . j , i . j . = i j • Nested loops (B i.j in outer, B u,v in inner loop, B h is loop header of inner loop): p ( i . j , u . v ) x ≤ h 15

Modeling Caches with IPET Discussion § Shown example: direct mapped instruction cache § Elegant way to integrate exec-time modelling into WCET calculation. § Approach can be extended to: • n-way set-associative instruction caches; • Interprocedural calls; • data caches; § Complexity: • Set of IPET constraints becomes much bigger due to CCG. • Time to solve IPET can take several hours !!! à Not feasible for real-size programs. 16

Summary Precise static WCET analysis requires an accurate exec-time model. Modeling of features like caches or pipelines. Precise and accurate exec-time modeling can result in complex models. 17

http://ti.tuwien.ac.at/rts/teaching/courses/wcet http://www.wcet.at 18