Modeling Hardware Timing 1 Caches and Pipelines Peter Puschner - - PowerPoint PPT Presentation

Modeling Hardware Timing 1 Caches and Pipelines

Peter Puschner

slides: P. Puschner, R. Kirner, B. Huber

VU 2.0 182.101 SS 2016

Generic WCET Analysis Framework

2

source code

• bject

code

Compilation Transformation of Flow Facts Extraction of Flow Facts Exec-Time Modeling

WCET

Calculation of Execution Scenarios

Exec-Time Modeling

Exec-time modeling typically done before WCET calculation in separate phases:

• 1. cache analysis
• 2. pipeline analysis
• 3. path analysis + WCET calculation

Above phases may be also combined to improve accuracy: Example:

(1)cache analysis (2) pipeline analysis + path-based WCET calculation.

3

Modeling Pipelines

Instruction timing represented by reservation tables:

4

IF ID EX M F WB IF ID EX M F WB

Modeling Pipelines

Basic operations on reservation tables: Sequential combination of two reservation tables

5

IF ID EX M F WB IF ID EX M F WB IF ID EX M F WB

Modeling Pipelines

Basic operations on reservation tables: Parallel combination of two reservation tables

6

IF ID EX M F WB IF ID EX M F WB IF ID EX M F WB

Modeling Caches

Types of caches:

• Instruction cache;
• Data cache;
• Unified cache (instruction + data);

Cache layout:

• direct mapped;
• n-way set-associative cache;

Replacement strategies:

• LRU (SPARC),
• pseudo-round robin

(ColdFire MFC 5307, PPC 750/755)

7

Modeling Caches (2)

Two approaches are presented:

1.

Cache analysis integrated into IPET-based path analysis, resulting in the following phases:

1.

pipeline analysis

2.

cache analysis + path analysis + WCET calculation

2.

Cache analysis as a separate phase using abstract interpretation (data-flow analysis), resulting in the following phases:

1.

cache analysis

2.

pipeline analysis

3.

path analysis + WCET calculation

8

Direct Mapped Cache

9

Line is selected by ld(m) address bits Line 1 Line 2 Line m m lines Line: valid bit (v), tag and data (k bytes) ... v w1 w2 wk tag tag

ld(m) bits

address word

ld(k) bits

Modeling Caches with IPET

here: Direct mapped instruction cache

§

Each basic block Bi is divided into {Bi.1, Bi.2,…,Bi.ni} l-blocks (cache line blocks).

§

Two l-blocks can be

• conflicting: they map to the same cache line and overwrite

the cache content of the other

• non-conflicting: they do not interfere in cache

§

Execution counter xi of Bi is divided into xi = xi.j

hit + xi.j miss, 1 ≤ j ≤ ni

§

ILP goal function:

∑∑

= =

⋅ + ⋅

N i n j miss j i miss j i hit j i hit j i

i

t x t x

1 1 . . . .

) (

10

Modeling Caches with IPET

B1 B2 B3

Ca che L ine 1 2 3

Cac he line 1 2 3 B1 B1 B1 B3 B3 B2 B2 B asic B loc k

B1.1 B1.2 B1.3 B2.1 B2.2 B3.1 B3.2

(i) CFG (ii) Ca che table

11

[Y.T.Steven Li,S.Malik,A.Wolfe,95]

basic block cache line block (l-block)

Modeling Caches with IPET

1

. .

≤ +

miss n m miss l k

x x

12

1

.

≤

miss l k

x

Cache Constraints:

• only one l-block Bk.l maps to the same cache

line (first access is miss):

• only two or more non-conflicting l-blocks

map to the same cache line (first access is miss):

• two or more conflicting l-blocks à use CCG

Modeling Caches with IPET

13

• A CCG (cache conflict graph) is constructed

for each cache line containing two or more conflicting l-blocks.

• The sum of control flow going in the node

must be the same as going out of the node:

1 ) . , ( : . ) . , . ( ) . , . (

, , ,

= = =

∑ ∑ ∑

v u v u v u i

v u s p

• nce
• nly

exec program v u j i p j i v u p x

Modeling Caches with IPET

B7.1 B4.1 s e

1 p(s,7.1) 0 p(s,e) 0 p(s,4.1) 0 p(4.1,e) 9 p(4.1,7.1) 9 p(7.1,4.1)

p(4.1,4.1)

0 p(7.1,7.1) 1 p(7.1,e) 91

(ii) CCG

14

B1 B2 B3 B5 B6 B8 B9 B7 B4B4.1

B7.1

1 c1 11 c 2 10 c3 10 c8 1 c9 1 c 5 11 c 6 9 c4 10 c7

(i) CFG

CFG and its corresponding CCG:

[Y.T.Steven Li,S.Malik,A.Wolfe,95]

these two lblocks are in conflict with each other (but with no other lblocks) à separate CCG for each conflict set

Modeling Caches with IPET

( ) ( ) ( )

j i j i p j i s p x j i j i p

hit j i

. , . . , . , .

.

+ ≤ ≤

h

x v u j i p ≤ ) . , . (

( )

j i j i p xhit

j i

. , .

. =

15

• bounding the cache hit frequency xi.jhit:

if an l-block Bi,j has only a local lifetime above constraints can be simplified as:

• Nested loops (Bi.j in outer, Bu,v in inner loop,

Bh is loop header of inner loop):

( ) ( ) ( )

e j i ExistsEdge j i s ExistsEdge , . . , ∧ ¬

Modeling Caches with IPET

Discussion

§

Shown example: direct mapped instruction cache

§

Elegant way to integrate exec-time modelling into WCET calculation.

§

Approach can be extended to:

• n-way set-associative instruction caches;
• Interprocedural calls;
• data caches;

§

Complexity:

• Set of IPET constraints becomes much bigger due to CCG.
• Time to solve IPET can take several hours !!!

à Not feasible for real-size programs.

16

Summary

Precise static WCET analysis requires an accurate exec-time model. Modeling of features like caches or pipelines. Precise and accurate exec-time modeling can result in complex models.

17

http://ti.tuwien.ac.at/rts/teaching/courses/wcet http://www.wcet.at

18