Memory Management
Marco Serafini
COMPSCI 532 Lecture 12
Memory Management Marco Serafini COMPSCI 532 Lecture 12 - - PowerPoint PPT Presentation
Memory Management Marco Serafini COMPSCI 532 Lecture 12 Announcements Project 2 published Info on website GitHub repo on Piazza Deadline: November 7 Next class: hands-on session Threads, processes, sockets,
COMPSCI 532 Lecture 12
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Global vars Stack Heap free space 0000…0000 FFFF….FFFF
void foo (int i) { int x = i; int * z = new int; *z = i; } x in stack *z in heap
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Global vars Stack Heap free space 0000…0000 FFFF….FFFF
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Fast memory
(small, expensive)
Slow memory
(large, cheap) Cache recently read data Evict inactive data
General pattern
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Fast memory
(small, expensive)
Slow memory
(large, cheap) Cache recently read data Evict inactive data
General pattern Virtual Memory
Fast Physical Memory (RAM) Slow Disk
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1 … … … … … … 264-1 access physical address access disk location, cache in main memory, return CPU executes store/load
address actual data actual data
Address translation virtual à physical Virtual Address Space (one separate per process) 1 2 3 3 OR Each byte has a 64 bit VIRTUAL address. Data layout as seen by the program (virtual)
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Caches Main memory Disk Swap
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1. Group contiguous virtual addresses in a block…
2. Store each virtual address separately…
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page address A A+O Page table address + (P * size(row))
P O … … … byte for V … 212-1 Memory page P 212 = 4096 bytes = 4 KB
virtual address V 12 bit 52 bit page offset page number … … A dirty? disk? .. Page table (one separate per process) 1 2
2 main memory accesses (if page in main memory)
Page address Control bits Page table address
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address soon thereafter
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1. Get the disk position from the page table 2. Invoke the OS to fetch page from disk (swap file) 3. Store the page in memory, update page table 4. Return memory address
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1. Keep an “accessed” control bit 2. Periodically reset it 3. Pages that were not accessed can be removed
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CPU MMU TLB Bus
CPU accesses virtual addresses MMU accesses physical addresses (directly)
CPU package Main memory Disk controller
Page table cache MMU implements address translation
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page address A A+O Page table address + (P * size(row))
P O … … … byte for V … 212-1 Memory page P 212 = 4096 bytes = 4 KB
virtual address V 12 bit 52 bit page offset page number … … A dirty? disk? .. Page table (one separate per process) 1 2 Page address Control bits Page table address
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PC + (P2 * size(row)) (chunk could be on disk) Page directory address + (P1 * size(row))
P1 P2 O 12 bit 52 bit page offset page number PC Page directory (separate per process) 1 2 A dirty? disk? .. Page table chunk (separate per process) A + O (page could be
disk) 3 Page table address Page address Control bits virtual address V
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A+O Page table address + (hash (P) mod N) must consider hash collisions
P O … … Byte for V … 212-1 Memory page P 212 = 4096 bytes = 4 KB
12 bit 52 bit page offset page number A dirty? disk? .. Inverted page table (separate per process) 1 2 keeps only N elements needs additional data structures to track pages on disk (not depicted) Page address Control bits virtual address V
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