Managing Risk in Block Based Designs: A Front End Acceptance - PDF document

Managing Risk in Block Based Designs: A Front End Acceptance Methodology Kumar Venkatramani and Stefanus Mantik 22-23 April 2002 1 CADENCE DESIGN SYSTEMS, INC. Front-End Acceptance A methodology for the analysis of a proposed chip design consisting of various functional blocks that enables the design team to determine the integrity of design data, evaluate associated design risks, and develop design budgets and plans 2 1

Outline • Block-Based Design Overview • Front End Acceptance Flow • Conclusion 3 Block-Based Design Overview Front End Acceptance Front End Acceptance Chip Design Planning Verification Verification Block Design Block Design Chip Assembly Chip Assembly 4 2

Block-Based Design (BBD) RTL RTL Clock Architecture Interconnect Arch. • Up to 1.5 M Gates • Physical Level Test Architecture • Soft, Firm Power Architecture Hard Chip Assembly Synthesis Block Authoring Place & Route IP Import Collars Legacy Block GDS II GDS II 5 Verification of BBD INPUTS •VC Signoff Field of Use •Spec. Verification •Input Req. Signoff Front end Acceptance •Authoring Pre-staged •Legacy Repeatable •verification Blocks •3rd party VC Methodology •chip assembly •tools/flows Pre-staged •Clocking •Power design plans •Bus •Test •Timing Predictable schedule, cost & Low risk performance 6 3

Field of Use • Digital CMOS • Synchronous ( ~ 80 MHz) • .25 → .18 µ technologies – multiple clock domains: All domains are integral multiples of the lowest • 150K → 1.5 M gates freq. domain • A/MS blocks restricted to: • Multiple levels of hierarchy – blocks specified by VSI 1.0, A/M-S – deal with only two at one time VSI Extension • Embedded bus architecture – e.g., PLLs, A/D, D/A, and hard – not pre-designed blocks – no previous layout (I.e custom) • Import cores, mc, and mp as • single or mixed voltages for A/MS hard or firm; blocks only • Technology rules, cell libraries, • Blocks created using enhanced TDD hard blocks, memory generators process for both VHDL and Verilog and data path blocks are fully defined and qualified 7 Front End Acceptance Purposes • Align expectations of system designers and chip design teams • Ensure that all required data to complete the chip design has been assembled • Develop program commitments with associated risk factors : – Cost – Engineering & Manufacturing – Schedule – Functionality – Performance, area, power • Create project data management environment – File structures, access control, release control, version control 8 4

Front End Acceptance Flow Customer Data & Specifications FEA Preparation Customer Data Validation Design Feasibility Assessment Meet No Renegotiate Specification Requirements? or Terminate Project Yes Project Planning and Design Budgeting To Chip Planning and Design and Project Data Block Design 9 Field of Experience (FOE) Database • The development and use of the BBD field of experience database involves the following processes: – Data gathering – Draws on prior designs to obtain FOE data – Can include projected data as well as actual data – Data classification – Groups data by application and design characteristics into an FOE database – Data certification – Verifies the data – Establishes the error of estimation during the FOE building and refinement stages – FOE data certification involves two level – Certification of completeness – Certification of accuracy – Data application – Use of the data to assess a design – Requires combining similar classifications to obtain statistically meaningful results 10 5

Front End Acceptance Flow Customer Data & Specifications Customer Data Validation Design Feasibility Assessment Meet No Renegotiate Specification Requirements? or Terminate Project Yes Project Planning and Design Budgeting To Chip Planning and Design and Project Data Block Design 11 Customer Data Validation • Formal handoff of design files and requirements from system designers (customers) to chip design teams • Project Checklist • Simulate chip level functional model with chip testbench – Documentations – Specifications • Simulate interconnected block functional models with chip – Test benches testbench – Libraries – Models • Data Completeness – Readability – Execution readiness – Conforms to design style 12 6

Example Tool Flow for Data Checking Chip Structural Chip Model (.v) Testbench (.v) Block RTL Block Chip Functional Model (.c or .v) (.v) Testbench (.v) Synthesizability Testability Check Block Power Compile Check TurboCheck-RTL Estimation NC-Verilog, NC-VHDL, Build Gates Verifault-XL Watt Watcher Or C compiler Elaboration ncelab Waveform Simulation Review ncsim SimVision Testbench Grading VeriSure No Customer Negotiation Results OK? and Clarification Yes Continue with Design Process 13 Select Preliminary Blocks • Review block specifications against customer requirements – Functionality – Performance – Cost – Support • Block selection matrix – Focus on Block characteristics within chip context • Validate block claims & assumptions • Can use IP Management Systems as a starting point to extract metadata about the blocks 14 7

Create Project Directories • Hierarchical project directory • Design directory hierarchy reflects design hierarchy – Store all customer data • Release control mechanism – Store all design data and directories – Capture all data to recreate • Version control project – Libraries • Access control – Designs – Utilities – Specifications – Scripts – Testbenches 15 Project Directory Structure proj ... de project_name project_name bin etc man ... etc rls reflib bin docs design_name design_name ... ... ... tool_ tool_ release_ release_ phys_ phys_ from_cust to_cust RCS work db_1 db_’n’ tag_1 tag_’n’ view_1 view_’n’ ... ... ... ... design_ design_ design_ design_ name-1 name-’n’ name-1 name-’n’ [Tar’d files for every design received and src bin etc docs lib reports every design released, including every customer’s version of a design] Staging Area For "release_tag_1" [Specific module & released tag’d data is copied from RCS Released & to the staging area - lower level designs can link to these Promoted Data directories for their source data, when required ] 16 8

Front End Acceptance Flow Customer Data & Specifications Customer Data Validation Design Feasibility Assessment Meet No Renegotiate Specification Requirements? or Terminate Project Yes Project Planning and Design Budgeting To Chip Planning and Design and Project Data Block Design 17 Design Feasibility Assessment • Analysis of a proposed design to determine the risks in accepting the design • Applied first at the Block level • Then applied at the Chip level • Three levels of refinements – Coarse Grain – Medium Grain – Fine Grain • Assess key project parameters – Cost – Performance – Power – Area 18 9

Design Feasibility Assessment • Block Level • Chip Level – Coarse Grain Assessment – Coarse Grain Assessment – Based on designer experience – Simple summation of block data – Relative to prior designs – Using soft block info – ~50% error margin – Medium Grain Assessment – Medium Grain Assessment – Weighted block assignments – Based on : – Statistical Analysis of routing area – equations – Use firm block info where available – database – Fine Grain Assessment – company field of use – ~20% error margin – Harden critical blocks – Fine Grain Assessment – Dipping Process – <5% error margin 19 Block Assessment Process Risk Model Initial Estimates Design Specifications Coarse Grain Assessment No Decision Quality Results Refine Fail Pass Medium Grain Assessment No Decision Quality Results Assessment Refine Fail Pass Design Fine Grain Assessment Fail Reject Accept Pass 20 10

Chip Assessment • Assessments performed with mixed granularity for the different elements : – 1st pass – Hard Blocks - Fine – Firm - Medium/Fine – Soft- Coarse/Medium – Authored - Coarse – Interconnect - Coarse – Subsequent Passes – Assign weighting factors to blocks based on criticality – Refine granularity on a block by block basis based on impact on total design 21 Chip Assessment Process Block Choice #1 Block Choice #2 Block Choice #3 Gather … Block Select … Refine … As Is … Estimates Assess System Global Refinement 22 11

Front End Acceptance Flow Customer Data & Specifications Customer Data Validation Design Feasibility Assessment Meet No Renegotiate Specification Requirements? or Terminate Project Yes Project Planning and Design Budgeting To Chip Planning and Design and Project Data Block Design 23 Project Planning and Design Budgeting • Develop detailed plans – Project schedule (precedence/dependencies, work breakdown) – Human resources – Machine resources – Cost/expenses 24 12