MALTA: an asynchronous readout CMOS monolithic pixel detector for - - PowerPoint PPT Presentation

▶
malta an asynchronous readout cmos monolithic pixel
SMART_READER_LITE
LIVE PREVIEW

MALTA: an asynchronous readout CMOS monolithic pixel detector for - - PowerPoint PPT Presentation

Feb 13, 2023 205 likes •653 views

MALTA: an asynchronous readout CMOS monolithic pixel detector for the ATLAS High-Luminosity upgrade. PIXEL 2018 - TAIPEI Roberto Cardella, Lluis Simon Argemi, Ivan Berdalovic, Florian Dachs, Valerio Dao, Leyre Flores Sanz De Acedo, Francesco

slide-1
SLIDE 1

PIXEL 2018 - TAIPEI

MALTA: an asynchronous readout CMOS monolithic pixel detector for the ATLAS High-Luminosity upgrade.

11/12/2018

1

Roberto Cardella, Lluis Simon Argemi, Ivan Berdalovic, Florian Dachs, Valerio Dao, Leyre Flores Sanz De Acedo, Francesco Piro, Tomasz Hemperek, Bojan Hiti, Thanushan Kugathasan, Cesar Augusto Marin Tobon, Konstantinos Moustakas, Ruth Magdalena Munker, Heinz Pernegger, Petra Riedler, Enrico Junior Schioppa, Abhishek Sharma, Walter Snoeys, Carlos Solans Sanchez, Tianyang Wang, Norbert Wermes, Piotr Rymaszewski, Ignacio Asensi Tortajada

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-2
SLIDE 2

PIXEL 2018 - TAIPEI

Outline

1. CMOS development for ATLAS ITk

  • TowerJazz 180nm technology

2. MALTA chip

  • Datapath: From the pixel to the output
  • Measurements results
  • Module design

3. Parallel R&D on MALTA 4. Conclusions

11/12/2018

2

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-3
SLIDE 3

PIXEL 2018 - TAIPEI

CMOS considered for ATLAS ITk

Outermost layer of ITk Pixel Barrel

  • 2016 quad modules
  • 3m2 (~45% of outer barrel layers)

For 4000 fb-1 integrated luminosity

  • TID = 80Mrad
  • NIEL 1.5 x 1015 neq/cm2

Monolithic CMOS sensors are considered as

  • ption for the outermost layer
  • Saves bump bonding for ~45% of outer barrel system
  • Substantial cost reduction and reduced module

assembly time

  • Requires “Drop-In” module compatibility to hybrid

module

11/12/2018

3

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-4
SLIDE 4

PIXEL 2018 - TAIPEI

Sensors in the TowerJazz 180 nm technology

Small collection electrode design with high resistivity (> 1 kΩ cm) p-type epitaxial layer (25 µm → MIP ~1500 e-) Deep p-well shielding n-well to allow full CMOS Reverse bias (~6 V): reduce input capacitance and increase depletion volume

4

Adding a planar n-type layer to improve depletion under the deep p-well near the pixel edges A fully depleted epitaxial layer results in faster charge collection and better radiation tolerance No circuit or layout changes required

  • W. Snoeys et al. https://doi.org/10.1016/j.nima.2017.07.046

Standard Process Modified Process

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-5
SLIDE 5

PIXEL 2018 - TAIPEI

Sensors in the TowerJazz 180 nm technology

Small collection electrode design with high resistivity (> 1 kΩ cm) p-type epitaxial layer (25 µm → MIP ~1500 e-) Deep p-well shielding n-well to allow full CMOS Reverse bias (~6 V): reduce input capacitance and increase depletion volume

5

Adding a planar n-type layer to improve depletion under the deep p-well near the pixel edges A fully depleted epitaxial layer results in faster charge collection and better radiation tolerance No circuit or layout changes required

  • W. Snoeys et al. https://doi.org/10.1016/j.nima.2017.07.046

Standard Process Modified Process

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

ALPIDE (standard process) will be installed in the new tracker system of the ALICE detector.

http://stacks.iop.org/1748-0221/11/i=02/a=C02042

slide-6
SLIDE 6

PIXEL 2018 - TAIPEI

Small collection electrode (TJ)

  • Small capacitance
  • Lower power
  • Less prone to coupling
  • Process modification for full depletion and

radiation tolerance increase

Large collection electrode (HV-CMOS)

  • Large capacitance
  • Higher power
  • Electronics in the input well, signal coupling
  • Practically uniform field
  • Very high radiation tolerance

p+ substrate nwell collection electrode pwell deep pwell nwell pwell nwe deep ll pwell NMO PMOS S p- epitaxial layer depletion boundary depleted zone low dose n-type implant p substrate pwell deep nwell collection electrode nwell PMOS NMOS depletion boundary depleted zone Substrate contact

Large vs Small collection electrode

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

6

slide-7
SLIDE 7

PIXEL 2018 - TAIPEI

Small collection electrode (TJ)

  • Small capacitance
  • Lower power
  • Less prone to coupling
  • Process modification for full depletion and

radiation tolerance increase

Large collection electrode (HV-CMOS)

  • Large capacitance
  • Higher power
  • Electronics in the input well, signal coupling
  • Practically uniform field
  • Very high radiation tolerance

p+ substrate nwell collection electrode pwell deep pwell nwell pwell nwe deep ll pwell NMO PMOS S p- epitaxial layer depletion boundary depleted zone low dose n-type implant p substrate pwell deep nwell collection electrode nwell PMOS NMOS depletion boundary depleted zone Substrate contact

Large vs Small collection electrode

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

7

slide-8
SLIDE 8

PIXEL 2018 - TAIPEI

TJ 2017 submission

11/12/2018

8

Talk on TJ-Monopix

Thu 13/12 12:00 I. D. Caicedo Sierra R&D status of the Monopix chips: Depleted monolithic active pixel sensors with a column-drain read-out architecture for the ATLAS Inner Tracker upgrade

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

Measurement results show improved non-ionizing radiation tolerance for sensors manufactured using the modified process

Analog front-end optimized for timing, based on ALPIDE

slide-9
SLIDE 9

PIXEL 2018 - TAIPEI

MALTA: Monolithic pixel detector from ALICE to ATLAS

11/12/2018

9

9

DACs for analogue biases digital periphery LVDS driver 18.6 mm

The 512x512 pixel - 8 sectors The front-end is a development from the ALPIDE one. Design based on a low-power analogue front-end and a novel asynchronous architecture to read out the pixel matrix

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-10
SLIDE 10

PIXEL 2018 - TAIPEI

The MALTA pixel

  • 2-3 um collection electrode → small input capacitance
  • 3.4 – 4 um separation between electrode and

electronics → low cross talk

  • 1 uW/pixel analog power (75 mW/cm²)
  • 10 mW/cm² digital power @ layer4

Sensor and analogue front-end (shaper-amplifier and discriminator) shielded from digital part to minimise crosstalk Time walk information preserved

sensor amplifier discriminator digital readout collection electrode analogue digital 36.4 µm 36.4 µm

11/12/2018

10

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-11
SLIDE 11

PIXEL 2018 - TAIPEI

Digital readout architecture

  • Front-end output injected into double-column

digital readout logic

  • Hits are stored using in-pixel flip-flops and

transmitted asynchronously over high-speed buses to the end-of-column logic (digital periphery)

  • No clock distribution over the active matrix –

reduces power consumption!

  • Double-column divided into groups of 2x8

pixels (“red” and “blue”)

  • Buses shared by all groups of the same colour

in the double-column, total of 64 groups

  • Each hit is hence represented by a 40 bit

word, asynchronously transmitted via parallel LVDS drivers

11/12/2018

11

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-12
SLIDE 12

PIXEL 2018 - TAIPEI

Digital readout architecture

  • Front-end output injected into double-column

digital readout logic

  • Hits are stored using in-pixel flip-flops and

transmitted asynchronously over high-speed buses to the end-of-column logic (digital periphery)

  • No clock distribution over the active matrix –

reduces power consumption!

11/12/2018

12

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

Factor 20 for matrix digital power More than 25% of total power

slide-13
SLIDE 13

PIXEL 2018 - TAIPEI

Asynchronous readout architecture

Hit signals from the pixels are buffered and arrive at the end-of-column with a maximum propagation delay of ~7.5 ns analogue output of

  • ne pulsed pixel

reference signal (measured by pulsing pixels on top, middle and bottom of the column) 25 ns = 17.5 ns (pulse) + 7.5 ns (signal)

11/12/2018

13

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-14
SLIDE 14

PIXEL 2018 - TAIPEI

Analogue front-end timing measurements

Time walk measurement performed with a 90Sr source using special pixels to monitor the analogue output With a threshold of 210 e- the in-time threshold is 300 e- (20% of MIP charge) Out-of-time hits due to charge sharing (measurement done on a single pixel) in-time threshold 130mV = 300 e-

  • ut-of-time hits 5.3%

(second hits in the cluster)

11/12/2018

14

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-15
SLIDE 15

PIXEL 2018 - TAIPEI

Front-end and readout timing measurements

Time walk can also be obtained by measuring the delay of digital output signals with respect to a fast trigger (scintillator) In-time efficiency for leading signals in clusters reaches 98% with a 300 e- threshold (no correction for the 7.5 ns propagation delay down the column)

11/12/2018

15

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-16
SLIDE 16

PIXEL 2018 - TAIPEI

  • Thres. dispersion and noise before and after TID

unirrad. 70 Mrad factor ~3 higher than simulation matches simulation RTS noise tail?

  • Increase in threshold spread

and noise under investigation

  • Front-end still
  • perational after 70

Mrad due to ELT in sensitive branch ELT RTS?

11/12/2018

16

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-17
SLIDE 17

PIXEL 2018 - TAIPEI

Efficiency in testbeam before and after irradiation

Decreasing threshold from ~600 e- to ~250 e- (unirrad.)

Unirradiated: lowering the threshold gives full efficiency

3

3 3

3 3 3

11/12/2018

17

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

Cannot go lower with threshold because of RTS noise and masking issue Solution for both under study.

slide-18
SLIDE 18

PIXEL 2018 - TAIPEI

Efficiency in testbeam before and after irradiation

Could not reach lower threshold (RTS + MASKING ISSUE)

Decreasing threshold from ~600 e- to ~250 e- (unirrad.)/350 e- (irrad.)

Unirradiated: lowering the threshold gives full efficiency Neutron irradiated 5x1014 neq/cm2 inefficiency in pixel corners due to low lateral electric field

3

3 3

3 3 3

11/12/2018

18

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-19
SLIDE 19

PIXEL 2018 - TAIPEI

Efficiency vs. deep p-well coverage

11/12/2018

19

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-20
SLIDE 20

PIXEL 2018 - TAIPEI

Efficiency vs. deep p-well coverage

  • Deep p-well only needed under n-wells of

PMOS transistors

  • In-pixel efficiency can be correlated to deep

p-well coverage around the collection electrode

  • Removed deep p-well results in higher
  • verall efficiency due to higher lateral

electric field

11/12/2018

20

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-21
SLIDE 21

PIXEL 2018 - TAIPEI

Pixel design improvements

11/12/2018

Additional “extra-deep p-well” layer

  • Already known by TowerJazz: no

process R&D needed Gap in the n- layer

  • requires only a change of the

existing mask for the n-layer

Talk on efficiency simulations

Mon 10/12 11:10 Ruth Magdalena Munker Simulations of CMOS sensors with a small collection electrode improved for a faster charge-collection and increased radiation tolerance

21

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

Magdalena Munker

After irradiation simulated current pulse

slide-22
SLIDE 22

PIXEL 2018 - TAIPEI

Mini MALTA pixel matrix

  • Pixel size: 36.4 μm x 36.4 μm
  • 64x16 pixel matrix includes 8 sectors with

splits on analogue front-end design, reset mechanism and process

Mini MALTA with synchronization and fixes for improved chargecollection

11/12/2018

22

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-23
SLIDE 23

PIXEL 2018 - TAIPEI

LAPA: pseudo-LVDS for the ATLAS Pixel Apparatus

11/12/2018

23

  • 280 X 240µm2 (2 pad pixel pitch)
  • Tunable DC current (7x 0.8mA )
  • Modular capacitive coupled pre-emphasis: 16 blocks

driving 25fF each.

  • Vcm feedback control at 0.8V.
  • External 100 Ω differential termination
  • 40 drivers integrated in MALTA (up to 2Gb/s)

Dedicated testchip 5Gb/s

280 µm 240 µm

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-24
SLIDE 24

PIXEL 2018 - TAIPEI

LAPA eye diagram

11/12/2018

24

5Gb/s 1.28Gb/s (ITk specification)

Jitterp-p= 71ps Jitterp-p= 38ps

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-25
SLIDE 25

PIXEL 2018 - TAIPEI

LAPA @1.28 Gbit/s on FLEX ITk prototype

11/12/2018

25

Flex for data transmission out of the ITk system (length~5m)

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-26
SLIDE 26

PIXEL 2018 - TAIPEI 11/12/2018

26

CMOS Quad-Module design

The ATLAS ITk sensors will be organized in quad modules. In the case of the hybrid pixel, one sensor

  • f around 4x4 cm2 will be bonded to four

2x2 cm2 front-end chips MALTA is the first large scale monolithic chip that allow build a compatible Quad-Module, assembling four detectors in a single FLEX

41.35mm 40.55mm chipA chipB chipD chipC

Under design

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-27
SLIDE 27

PIXEL 2018 - TAIPEI

Parallel R&D on MALTA

11/12/2018

27

Chip to Chip communication Flip chip connection

MALTA can transmit power and data asynchronously to a neighboring chip (via CMOS pad), merging the data of multiple pixel matrix in just one parallel output

Connection between neighboring chips using flip chip

  • Better for assembling
  • Allow additional electronics in the flipchip

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-28
SLIDE 28

PIXEL 2018 - TAIPEI

Buried channels cooling

11/12/2018

28

DOI: 10.1109/ITHERM.2012.6231493

  • J. Bronuzzi, A. Mapelli, R. Callegari, P. Riedler

(Ø 35 µm, length ≈ 1 cm) Flux direction

Sezione longitudinale

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-29
SLIDE 29

PIXEL 2018 - TAIPEI

Malta Telescope

6 MALTA chip-based planes 2 Scintillators 4um resolution

11/12/2018

29

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-30
SLIDE 30

PIXEL 2018 - TAIPEI

Conclusions

The MALTA CMOS pixel sensor was developed in view of the ATLAS High-Luminosity upgrade. The large pixel matrix implements a fast, low-power analogue front-end and a novel asynchronous readout architecture. The chip has been extensively characterised in lab measurements and testbeam, and shows promising results in terms of front-end performance and readout capability, but needs further improvement: The small collection electrode sensor suffers from degraded efficiency in the pixel corners after irradiation to 1015neq/cm2, and this is being addressed by means of improvements in the process (see

  • M. Munker’s presentation), and also in the front end design to obtain a lower threshold.

An LVDS driver has been designed and tested to transmit the data to the ITk readout system, up to 5Gb/s. The MALTA chip allows to build the first prototype of a monolithic module, compatible with the hybrid equivalent for the ITk system. Several R&D on monolithic pixel sensors are in progress using the MALTA chip, such as buried channels cooling and chip to chip data communication.

11/12/2018

30

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-31
SLIDE 31

PIXEL 2018 - TAIPEI

Thank you for the attention

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

31

Question time!

slide-32
SLIDE 32

PIXEL 2018 - TAIPEI

Backup slides

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

32

slide-33
SLIDE 33

PIXEL 2018 - TAIPEI

Time walk after irradiation

Little change in front-end signal and timing after irradiation (somewhat more charge sharing)

33

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-34
SLIDE 34

PIXEL 2018 - TAIPEI

Front-end optimization (simulation)

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

34

sensing node amplifier output discriminator output

pulse duration clipping (MALTA) dead time time walk

  • I. Berdalovic et al 2018 JINST 13 C01023

Charge threshold Qth 300 e Equivalent Noise Charge 7.1 e Channel-to-channel RMS 10.2 e Panalog = 0.9 μW

slide-35
SLIDE 35

PIXEL 2018 - TAIPEI

Efficiency after irradiation to 1015

15 neq eq/cm2

Decreasing threshold from ~450 e- to ~350 e- Artifact: pixel center efficiency decreases at low thresholds due to noise issues

11/12/2018

35

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-36
SLIDE 36

PIXEL 2018 - TAIPEI

Silicon Pixel Detector

11/12/2018

36

e e e e h h h h

PWELL PWELL NWELL DEEP PWELL NWELL DIODE NMOS TRANSISTOR PMOS TRANSISTOR Epitaxial Layer P- Substrate P++

Monolithic Hybrid

  • Used in current LHC detectors
  • Optimized silicon sensor for radiation hardness
  • Dedicated front-end electronics bonded to the

sensor

  • Thick modules
  • Complex and costly assembly due to fine-pitch

bump bonding

  • Promising technology for future detectors
  • Single chip integrate electronic and sensor
  • Radiation hardness limitation
  • Lower material budget
  • Large number of available vendors

ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

slide-37
SLIDE 37

PIXEL 2018 - TAIPEI

MALTA periphery logic

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

37

The MALTA periphery implements a fully asynchronous arbitration logic to merge the signals coming from groups with different colour In the case of simultaneous signals on two buses the logic gives priority to one, while the other is delayed Merging is repeated for all the double-columns in a binary tree-like structure, adding a column address bit in each step, until all outputs are merged into one parallel 40-bit bus … … x256 double-columns x10 levels of merging for full matrix

slide-38
SLIDE 38

PIXEL 2018 - TAIPEI

Asynchronous readout – measurements

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

38

Parallel data bus requires delay uniformity: all address bits need to arrive to the periphery at the same time as the reference signal pixel group column BCID reference sample=390 ps window (pulsing a pixel 200 times and

  • versampling

the output signals to check the timing alignment)

slide-39
SLIDE 39

PIXEL 2018 - TAIPEI

MALTA Read-out system

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

39

 Carrier board for two MALTA chips with FMC interface  Asynchronous oversampling on Xilinx VC707 board  Slow read-out through IPbus ethernet to Linux PC running SLC6  Fast read-out through GBT optical link with FELIX + ITK SW VC707 VC709

GBT SFP DAQ

FELIX

PCIe SFP

Custom FW

MALTA FMC FMC

Analog

Carrier board

Control and monitoring Eth

  • R. Cardella, V. Dao, C. Marin Tobon, E.J.Schioppa, B. Schlager, L. Simon Argemi, C. Solans Sanchez
slide-40
SLIDE 40

PIXEL 2018 - TAIPEI

LAPA Single Channel Schema

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

40 LVDS_IN_P<X> LVDS_IN_N<X> TR_EN CMOS_IN<X> LVDS_RX_EN LVDS_RX_EN LAPA_CMOS_DRIVER_SEL<X> LAPA_CMOS_DRIVER_SEL<X> CMOS_OUT<X> LVDS_OUT_P<X> LVDS_OUT_N<X>

slide-41
SLIDE 41

PIXEL 2018 - TAIPEI

LAPA H-BRIDGE

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

41

7 HBRIDGE blocks of 0.8mA - max: total 6mA

slide-42
SLIDE 42

PIXEL 2018 - TAIPEI

LAPA-PRE-EMPHASIS

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

42

16 BLOCKS driving 25fF coupled with the output pad

slide-43
SLIDE 43

PIXEL 2018 - TAIPEI

LAPA TESTCHIP SIMULATION

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

43

2.5GHz LVDS IN – LVDS OUT. 100Ω termination. 1pF load. Simulated jitter=45ps

slide-44
SLIDE 44

PIXEL 2018 - TAIPEI

LAPA

11/12/2018 ROBERTO CARDELLA ROBERTO.CARDELLA@CERN.CH

44

Preliminary power consumption

Expected static power consumption Measurements on test chip

Static+Dynamic 1.28Gb/s Current [mA] Power [mW] 5 Hbridge 6 10.8 7 Hbridge 8 14.4 Static Current [mA] Power [mW] 5 Hbridge 4 7.2 7 Hbridge 5.2 10