MajSynth An n -input Majority Algebra based Logic Synthesis Tool for - - PowerPoint PPT Presentation

SLIDE 1

MajSynth

An n-input Majority Algebra based Logic Synthesis Tool for QCA

.

Rajeswari Devadoss, Kolin Paul and M. Balakrishnan

presented by M. Balakrishnan, Professor, CSE, IITD

Department of Computer Science and Technology Indian Institute of Technology Delhi

SLIDE 2

A New Logic Gate

The 3-input Majority Gate . . M3 .

⟨x y z⟩

.

x

.

y

.

z

. More ‘1’s among inputs?

• 2-AND : ⟨x y 0⟩=x·y
• 2-OR : ⟨x y 1⟩=x+y
• More : ⟨x y z⟩=xy+yz+zx
• Quantum-dot Cellular Automata
• QCA Primary gate : 3-input Majority [1]
• 5-input and 7-input Majority gates [2]
• Other technologies : SET, TPL, STMG

Introduction Majority Gate Slide 1 of 15

SLIDE 3

Tweaked Logic Synthesis

. Pre-processing . Logic Minimization . Post-processing .

Boolean Algebra

for NOT & 2-AND, 2-OR . Existing Majority Synthesis . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

Introduction Logic Synthesis Slide 2 of 15

SLIDE 4

Tweaked Logic Synthesis

. Pre-processing . Logic Minimization . Post-processing .

Boolean Algebra

for NOT & 2-AND, 2-OR . Existing Majority Synthesis . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

Introduction Logic Synthesis Slide 2 of 15

SLIDE 5

Tweaked Logic Synthesis

. Pre-processing . Logic Minimization . Post-processing .

Boolean Algebra

for NOT & 2-AND, 2-OR . Existing Majority Synthesis . 3-input Majority Patterns .

3/4-var k-Map[3] [4] Genetic Algorithm[5] XOR[6] & BDD[7]

Introduction Logic Synthesis Slide 2 of 15

SLIDE 6

Tweaked Logic Synthesis

. Pre-processing . Logic Minimization . Post-processing .

Boolean Algebra

for NOT & 2-AND, 2-OR

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns .

3/4-var k-Map[3] [4] Genetic Algorithm[5] XOR[6] & BDD[7]

.

Introduction Logic Synthesis Slide 2 of 15

SLIDE 7

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . Need : Mathematics and Methods for Majority

Introduction Logic Synthesis Slide 3 of 15

SLIDE 8

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . First step : Develop the Mathematics

• f Majority

Boolean Algebra n-input Majority Overview

SLIDE 9

The n-input Majority Function

.

Mn

.

Mn=    1 if at least n+1

2

• f {w1, w2, . . . , wn} are ‘1’s
• therwise

.

w1

.

w2

.

• .
• .

wn

. Example : The 7-input Majority function ⟨a b c d e f g⟩=1 iff at least 4 of {a, b, c, d, e, f, g} are ‘1’s

• ⟨a b c d 03⟩=abcd
• ⟨a b c d3 1⟩=abc+d
• ⟨a b c d e3⟩=abcd+(a+b+c+d)e
• ⟨a b c d2 1 0⟩=abc+(a+b+c)d
• ⟨a b c2 d2 1⟩=(a+b)(c+d)+cd
• ⟨a b c d2 02⟩=(ab+bc+ca)d

Duplicates, constants among inputs : Different functions

Boolean Algebra n-input Majority Slide 4 of 15

SLIDE 10

Majority Law : Compaction

Implement a single Majority term with fewer inputs ⟨a b2 c3 d5 e6 e6

• Cancel

0 1

• Cancel

⟩= . . ⟨a b2 c3 d5⟩ = . . ⟨a b c d2⟩

• Compact redundant inputs

Conditions when term evaluates to ‘1’ . . ⟨a b2 c3 d5⟩ At least 11+1

2 =six ‘1’s

ad5, b2d5, c3d5, ab2c3 . . ⟨a b c d2⟩ At least 5+1

2 =three ‘1’s

ad2, bd2, cd2, abc Both implement ad+bd+cd+abc Solve ILP representing Majority term to minimize size

Boolean Algebra Majority Laws Slide 5 of 15

SLIDE 11

Majority Law : Flatten

AND(a, b, AND(c, d)

• Flatten

)=AND(a, b, c, d) OR(OR(a, b)

• Flatten

, OR(c, d)

• Flatten

)=OR(a, b, c, d) Flatten singleton n-input Majority: n+1

2

copies of other inputs xyz + xyz ⇒ ⟨ 1 ⟨02 x y z⟩

• Make 5+1

2 =3 copies

. . ⟨02 x y z⟩

• Flatten

⟩ =⟨13 ⟨02 x y z⟩3 02 x y z⟩

• Compact

= ⟨1 x y z ⟨02 x y z⟩3⟩

Boolean Algebra Majority Laws Slide 6 of 15

SLIDE 12

Majority Law : Distributivity

a·b· (c+d+e)

Distribute

=a·b·c+a·b·d+a·b·e Distribute at least n+1

2

inputs of a n-input Majority term xyz + xyz ⇒ ⟨1 x y z ⟨ . . 02 x . . y z ⟩3

• Distr. All

⟩ =⟨⟨1 x y z 03⟩2

• Compact

⟨1 x y z x3⟩

• Compact

⟨1 x y z y3⟩

• Compact

⟨1 x y z z3⟩

• Compact

⟩ =⟨ . . ⟨02 x y z⟩2 x ⟨1 x y2 z⟩ ⟨1 x y z2⟩⟩ [Distribute all inputs] =⟨ . . ⟨02 x y z⟩2 x

• from distr.

. . y z

• not distr.

⟩ [ Distribute (5+1)/2=3 inputs : 02, x ] Rank and choose inputs to distribute to simplify expression

Boolean Algebra Majority Laws Slide 7 of 15

SLIDE 13

Majority Law : Distributivity

a·b· (c+d+e)

Distribute

=a·b·c+a·b·d+a·b·e Distribute at least n+1

2

inputs of a n-input Majority term xyz + xyz ⇒ ⟨1 x y z ⟨ . . 02 x . . y z ⟩3

• Distr. 02,x

⟩ =⟨⟨1 x y z 03⟩2

• Compact

⟨1 x y z x3⟩

• Compact

⟨1 x y z y3⟩

• Compact

⟨1 x y z z3⟩

• Compact

⟩ =⟨ . . ⟨02 x y z⟩2 x ⟨1 x y2 z⟩ ⟨1 x y z2⟩⟩ [Distribute all inputs] =⟨ . . ⟨02 x y z⟩2 x

• from distr.

. . y z

• not distr.

⟩ [ Distribute (5+1)/2=3 inputs : 02, x ] Rank and choose inputs to distribute to simplify expression

Boolean Algebra Majority Laws Slide 7 of 15

SLIDE 14

Majority Law : Difference

Exploit Common and Differing (Negated) elements xyz + xyz=x(yz + yz) ⇒ ⟨⟨02 . . x . . y z ⟩2 . . x . . y z ⟩

• Diff : y,z; Common : x

=⟨⟨0 . . y z ⟩2 . . x . . y z ⟩ Beyond sum/product forms of common, differing elements xyz + xyz + xyz ⇒ ⟨1 . . x y . . z ⟨⟨0 y z⟩2 . . x y . . z ⟩3⟩

• Diff : x,y; Common : z

=⟨⟨⟨ . . . . y z⟩2 x . . y . . 1 ⟩2

• Diff : 0; Common : y

x y z⟩ =⟨⟨⟨1 x z⟩

Flatten

y 0⟩2x y z⟩

Boolean Algebra Majority Laws Slide 8 of 15

SLIDE 15

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . Next step : Use algebra to Minimize expressions

Logic Minimization Iterative Method Overview

SLIDE 16

Iterative Minimization : x ⊕ y ⊕ z

While reducible nodes available

• 1. Choose next node
• 2. Flatten if possible
• 3. Else Diff. if possible
• 4. Else Distr. if it simplifies
• 5. Compact node

Analysis

• Start : Ordered minterms
• Low scalability as no. of

minterms grow

• Reduction : Unrestricted

n-input Majority terms

M7+M4=⟨1 x y z ⟨02 x y z⟩3⟩

• Diff : y,z; Common :x

M2+M7,4=⟨1 x y z ⟨⟨0 y z⟩2 x y z⟩3⟩

• Diff : x,y; Common : z

=⟨ ⟨⟨0 y z⟩2 x y 1⟩2

• Diff : 0; Common : y

x y z⟩ =⟨⟨ ⟨1 x z⟩

Flatten : 2x

y 0⟩2x y z⟩ =⟨⟨1 x z y2 02⟩2

• Compact

x y z⟩ =⟨⟨0 x y2 z⟩2

• Distr y2,z

x y z⟩ =⟨0 x ⟨x y z⟩2 ⟨x y z⟩

Flatten : 2x

⟩ =⟨02 x2⟨x y z⟩4 x y z⟩

• Compact

M1+M2,7,4=⟨1 x y z⟨0 x y z ⟨x y z⟩3⟩3⟩

• Diff : 0; Common : x,y,z

M1,2,7,4=⟨x y z ⟨x y z⟩2⟩ M7,4,2,1=⟨x y z ⟨x y z⟩2⟩

Logic Minimization Iterative Method Slide 9 of 15

SLIDE 17

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . Next step : Apply gate size constraints

Post-processing Downsize Majority Overview

SLIDE 18

Downsizing 7-input Majority

Majority Counts .

X= {a, b, c, d}

.

Y= {e, f, g}

. .

1

.

2

.

3

.

4

.

X≥4

.

0 . 1

.

2

.

3

. .

1

.

2

.

3

.

4

.

X≥3

. .

1

.

2

.

3

.

Y≥1

. .

1

.

2

.

3

.

4

.

X≥2

. .

1

.

2

.

3

.

Y≥2

. .

1

.

2

.

3

.

4

.

X≥1

. .

1

.

2

.

3

.

Y≥3

.

. : ⟨a b c d 03⟩ . : ⟨a b c d 0⟩ . : ⟨e f g 02⟩ . : ⟨e f g⟩

.

. : ⟨a b c d 13⟩ . : ⟨a b c d 1⟩ . : ⟨e f g 12⟩

Downsizing M7=⟨ . . a b c d . . e f g ⟩ .

.

+

.

·

.

+

.

·

.

+

.

·

. =⟨ . . . . . . . ⟩ =⟨ . . ⟨ . . . . . ⟩⟩=⟨ . . ⟨ . . ⟨ . . . ⟩⟩⟩ =⟨a b c d ⟨ . . ⟨ . . . ⟩⟩3⟩ =⟨a b c d ⟨e f g ⟨ . . . ⟩2⟩3⟩ =⟨a b c d ⟨e f g ⟨a b c d ⟨e f g⟩⟩2⟩3⟩

Downsizing T1=⟨ . . a b c . . d T3

2 ⟩

.

.

+

.

·

.

+

.

·

.

+

.

·

. = .

+

.

·

.

+

.

·

. [ . = . ; .

+

. = . ] =⟨ . . . . . ⟩=⟨ . . ⟨ . . . ⟩⟩ =⟨d T2 ⟨ . . . ⟩⟩=⟨d T2 ⟨a b c T2

2⟩⟩

Partition determines downsizing

Post-processing Downsize Majority Slide 10 of 15

SLIDE 19

Downsizing 7-input Majority

Majority Counts .

X= { d, T3

2

}

.

Y= {a, b, c}

. .

1

.

2

.

3

.

4

.

X≥4

.

0 . 1

.

2

.

3

. .

1

.

2

.

3

.

4

.

X≥3

. .

1

.

2

.

3

.

Y≥1

. .

1

.

2

.

3

.

4

.

X≥2

. .

1

.

2

.

3

.

Y≥2

. .

1

.

2

.

3

.

4

.

X≥1

. .

1

.

2

.

3

.

Y≥3

.

. : ⟨d T2 0⟩ . : ⟨T2⟩ . : ⟨a b c 02⟩ . : ⟨a b c⟩

.

. : ⟨d T2 1⟩ . : ⟨T2⟩ . : ⟨a b c 12⟩

Downsizing M7=⟨ . . a b c d . . e f g ⟩ .

.

+

.

·

.

+

.

·

.

+

.

·

. =⟨ . . . . . . . ⟩ =⟨ . . ⟨ . . . . . ⟩⟩=⟨ . . ⟨ . . ⟨ . . . ⟩⟩⟩ =⟨a b c d ⟨ . . ⟨ . . . ⟩⟩3⟩ =⟨a b c d ⟨e f g ⟨ . . . ⟩2⟩3⟩ =⟨a b c d ⟨e f g ⟨a b c d ⟨e f g⟩⟩2⟩3⟩

Downsizing T1=⟨ . . a b c . . d T3

2 ⟩

.

.

+

.

·

.

+

.

·

.

+

.

·

. = .

+

.

·

.

+

.

·

. [ . = . ; .

+

. = . ] =⟨ . . . . . ⟩=⟨ . . ⟨ . . . ⟩⟩ =⟨d T2 ⟨ . . . ⟩⟩=⟨d T2 ⟨a b c T2

2⟩⟩

Partition determines downsizing

Post-processing Downsize Majority Slide 10 of 15

SLIDE 20

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . Optimization : Handle Symmetric functions

Pre-processing Symmetric Functions Overview

SLIDE 21

Symmetric Function : 7-input XOR

Majority Counts . S= {m, n, o, p, q, r, s} .

0 . 1

.

2

.

3

.

4

.

5

.

6

.

7

.

S≥7

. .

1

.

2

.

3

.

4

.

5

.

6

.

7

.

S≥5

.

S≤5

. .

1

.

2

.

3

.

4

.

5

.

6

.

7

.

S≥3

.

S≤3

. .

1

.

2

.

3

.

4

.

5

.

6

.

7

.

S≥1

.

S≤1

.

. = ⟨m · · · s06⟩ . = ⟨m · · · s02⟩ . = ⟨ ¯ m · · ·¯ s04⟩ . = ⟨ ¯ m · · ·¯ s⟩

.

. = ⟨m · · · s16⟩ . = ⟨m · · · s12⟩ . = ⟨ ¯ m · · ·¯ s14⟩

X7=xor(m, n, o, p, q, r, s) .

.

+

.

·

.

+

.

·

.

+

.

·

. =⟨ . . . . . . . ⟩ =⟨ . . ⟨ . . . . . ⟩⟩=⟨ . . ⟨ . . ⟨ . . . ⟩⟩⟩ =⟨m n o p q r s ⟨ . . ⟨ . . . ⟩⟩6⟩ =⟨m · · · s ⟨ ¯ m · · ·¯ s ⟨ . . . ⟩4⟩6⟩ =⟨m · · · s ⟨ ¯ m · · ·¯ s ⟨m · · · s ⟨ ¯ m · · ·¯ s⟩2⟩4⟩6⟩

Symmetry ⇒ More minterms

• Symmetric functions : bypass

iterative minimization

• Symmetric sub-function + fewer

minterms for iter. min.

Pre-processing Symmetric Functions Slide 11 of 15

SLIDE 22

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns . Final : Decompose along Symmetry

Pre-processing Decomposition Overview

SLIDE 23

Graph Decomposition : 3-feasible Vs 4-feasible

MALS[3] : decompose graph to 3-feasible nodes using SIS MajSynth : decompose graph to 4-feasible (or larger) nodes . . .

−6

.

−4

.

−2

. .

2

.

4

.

6

.

8

.

10

. .

20

.

40

.

MALS Vs MajSynth : Savings in no. of 3-Maj in 4-var functions

.

• No. of Classes

. . .Better . .Same . .Worse . 88 . 15 . 39 Savings not as expected on graphs of 4-feasible nodes . . .

c m 8 2 a

.

c m 8 5 a

.

z 4 m l

.

c u

.

c c

.

c 8

.

c m 1 6 3 a

.

9 s y m m l

.

f r g 1

. .

100

.

200

.

300

.

MALS Vs MajSynth : MCNC Benchmarks 4-decomposed using SIS tool

.

• No. of 3-Maj Gates

. . .MALS . .MajSynth

Pre-processing Decomposition Slide 12 of 15

SLIDE 24

Symmetry Decision Diagrams

Preserve Symmetry in Boolean Graph representation

• Binary Decision Diagram ⇒ Symmetry Decision Diagram
• Each node branches on values of a set of variables
• One branch for each ON-count : 0, 1, . . . , no. of vars

. . F . 1 .

3

. 1 .

2

. .

1

. . .

{a, b, c} (a) F=⟨a b c⟩

. . F . 1 .

3

. .

2

. 1 .

1

. . .

{a, b, c} (b) F=a⊕b⊕c

. . F . F3 .

3

. F2 .

2

. F1 .

1

. F0 . .

{a, b, c} (c) F symm in {a, b, c}

F symm. in S= {a, b, c} : ⟨S3S≥3(S≥2·F2+S≥2·F1)(S3·F3+S≥1·F0)2⟩ Multiple levels of partial symmetry represented as SDD

Pre-processing Decomposition Slide 13 of 15

SLIDE 25

SDD to Majority

. F . 1 .

3

. G . 1 .

3

. 1 .

2

. .

1

. . .

2

. G . 1 .

3

. 1 .

2

. .

1

. . .

1

. . .

{x, y, z}

.

{a, b, c}

.

{a, b, c} (a) F=⟨x y z G2⟩ and G=⟨a b c⟩

. . F . G . 1 .

3

. 1 .

2

. .

1

. . .

2

. G . .

3

. .

2

. 1 .

1

. 1 . .

1

. G . 1 .

3

. 1 .

2

. .

1

. . . .

{x, y}

.

{a, b, c}

.

{a, b, c}

.

{a, b, c} (b) F=x⊕y⊕G and G=⟨a b c⟩

. . F . F3 . 1 .

2

. .

1

. . .

3

. .

2

. .

1

. F0 . 1 .

2

. 1 .

1

. . . .

{x, y, z}

.

{a, b}

.

{a, b}

. F . 1 .

3

. 1 .

2

. .

1

. . .

{a, b, D}

.

= ⇒

. where D=⟨x y z 02⟩, D=⟨¯ x¯ y¯ z 02⟩

(c) F=xyzab+¯ x¯ y¯ z(a+b)=⟨⟨x y z 02⟩⟨¯ x¯ y¯ z 02⟩⟨a b ⟨¯ x¯ y¯ z 02⟩⟩⟩

Pre-processing Decomposition Slide 14 of 15

SLIDE 26

Symmetry Aware Graph Decomposition

• Find Symmetry Groups using CUDD tool
• Order Symmetry Groups using heuristic
• Construct SDD with leaves - ‘1’, ‘0’, and non-symmetric nodes
• Internal nodes : Minimize using Majority counts
• Leaf nodes : 3-decompose and minimize iteratively

. . .

c m 8 2 a

.

c m 8 5 a

.

z 4 m l

.

c u

.

c c

.

c 8

.

c m 1 6 3 a

.

9 s y m m l

.

f r g 1

. .

100

.

200

.

3-feasible+MALS[3] Vs Symm-decomposed+MajSynth : MCNC Benchmarks

.

• No. of 3-Maj Gates

. . .MALS[3] . .3-MajSynth Decompose for Symmetry to exploit Majority

Pre-processing Decomposition Slide 15 of 15

SLIDE 27

MajSynth : n-input Majority Algebra based Synthesis

.

Graph Decomposition

.

Pre-processing Symmetry

. Logic Minimization

n-input Majority

. Post-processing

Downsize Majority

.

Boolean Algebra

for NOT &

n-input Majority

. Existing Majority Synthesis . 3-input Majority Patterns . 3-input Majority Patterns .

3/4-var k-Map[3][4] Genetic Algorithm[5] XOR[6] & BDD[7]

. 3-input Majority Patterns .

MajSynth

A framework for Majority Synthesis

Conclusion MajSynth Overview

SLIDE 28

References I

[1] Craig S Lent and P Douglas Tougaw. “A device architecture for computing with quantum dots”. In: Proceedings of the IEEE 85.4 (1997),

• pp. 541–557.

[2] Keivan Navi, Amir Mokhtar Chabi, and Samira Sayedsalehi. “A Novel Seven Input Majority Gate in Quantum-dot Cellular Automata.” In: International Journal of Computer Science Issues (IJCSI) 9.1 (2012). [3] Rui Zhang, P. Gupta, and N.K. Jha. “Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies”. In: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 26.7 (July 2007), pp. 1233–1245. [4] Peng Wang, Mohammed Niamat, and Srinivasa Vemuru. “Minimal majority gate mapping of 4-variable functions for quantum cellular automata”. In: Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference

• n. IEEE. 2011, pp. 1307–1312.

SLIDE 29

References II

[5] MR Bonyadi et al. “Logic optimization for majority gate-based nanoelectronic circuits based on genetic algorithm”. In: Electrical Engineering, 2007. ICEE’07. International Conference on. IEEE. 2007,

• pp. 1–5.

[6] David Y Feinstein and Mitchell A Thornton. “ESOP transformation to majority gates for quantum-dot cellular automata logic synthesis”. In: Proceedings of the Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RMW). 2007, pp. 43–50. [7] Luca Amarú, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “BDS-MAJ: A BDD-based logic synthesis tool exploiting majority logic decomposition”. In: Proceedings of the 50th Annual Design Automation Conference. ACM. 2013, p. 47.