Main aspect s of CMOS t echnology scaling forming int erconnect - PowerPoint PPT Presentation

� Main aspect s of CMOS t echnology scaling forming int erconnect reliabilit y t hreat s: � Reduction of interconnect width, spacing and thickness, due to scaling. � Integration of low- k dielectrics for interconnect capacitance reduction and crosstalk avoidance => higher performance. � S aturation of operating voltage around 1.0V in the state-of-the art deep sub-micron technologies. � Reduction of inter-metal wire pitch, rising the inter-metal electric field. � Thermal hotspots, due to the rise of operating frequency and leakage power. � Reliability phenomena of progressive nature in transistors and interconnects gain in significance . � Interconnect reliability-aware design methodologies are strongly motivated .

� Degradation of interconnect electrical and physical characteristics => wires’ delay rise over time. Past abrupt failures � Such dominant mechanisms are: � Electro-migration (EM) : Transport of Cu atoms by free electrons from wires' anode to the cathode => progressive void formation and interconnect resistance rise. � Stress-migration (SM) : Abrupt changes of the chip’ s temperature => tensile stresses on interconnects => increased resistance and inter-metal capacitance. Parametric � Time-Dependent Dielectric Breakdown (TDDB) : Rising elect ric field due t o scaling => gradual dielect ric damage due t o conduct ive pat hs in failures int er-met al wires => wire charging/ discharging delay overhead . � Progressive system’ s performance drift due the increased wire T = 275 °C delay (timing failures). J = 20 mA/ μ m 2 � Move to system-level timing/ parametric failures => Product’ s lifetime shrinking. Stress conditions parameters � Need to estimate mating the timing impact of BEOL int erconnect reliabilit y wear-out s on wires and also on t he syst em/ product over t ime.

Path 1 F/F •30% increased delay due to std. cell inter-metal leakage in the F/F black-colored wire => 30% delay rise! std. cell From individual wires’ to Timing violation due to design’ s performance shifting => std. cell std. cell F/F TDDB ! System-level timing failures before the expected product’s lifetime ! •Path 1 has more timing Path 2 slack than Path2, due to TDDB-induced delay overhead. Timing violation on Path2 ! •Timing failures of TDDB dependent on operating Path 1 delay conditions ( V dd , T ), Path 2 delay functionality, wirelength and clock period inter-metal spacing. Critical slack2 path delay slack1

� Estimation of gradual timing impact of TDDB on wires due to inter-metal dielectric (IMD) leakage. � Capturing of the individual wires’ delay overhead on target system’ s performance. � Inter-metal leakage extrapolated from stress to operating conditions, to achieve: � Accurate estimation of wires’ delay overhead, regardless of the TDDB model. � Independence from the given experimental data coverage. � Predict ion of syst em’ s performance drift over t ime (syst em’ s lifet ime est imat ion). � Considerat ion of a chip’ s t emperat ure profile from realist ic soft ware applicat ions, as: � TDDB is st rongly dependent on t emperat ure. � A const ant and uniform t emperat ure for t he ent ire chip is unrealist ic. � Est imat ion of t he impact of TDDB on design’ s t iming considering different place-and-rout e scenarios.

Time-Dependent Dielectric Breakdown (TDDB): Gradual inter-metal dielectric drift in between wires of the same layer => progressive formation of conductive paths => possibly, unwanted short-circuits. Four phases for the formation of Dominant TDDB models : inter-metal dielectric conductive � E-model paths. No consensus on the � 1/ E-model Orange circle : temporarily trapped model ! � Our approach : Inter-metal l eakage charge (hole). ext rapolat ion from accelerat ed t o Green circles : permanently operat ing condit ions (V dd . T) trapped charges (electrons). IMD leakage of low-k dielectrics due to TDDB impacts progressively: � Individual wires’ delay. � Temperature in specific layout regions Does TDDB gradually affect due to leakage’ s flow. the system’s performance also IMD leakage due to TDDB � Possibly, the design’ s functionality ? between adjacent inter-metal (short-circuits).

1 - Timing Path S election 2 - Temperature profiling 3 – Extraction of nets & of their wires 4 – Wires’ delay computation due to TDDB 5 – Delay back- annotation and evaluation The proposed RTL2GDS II-based temperature-aware TDDB analysis flow.

Platform-based application Post-Layout Post-layout Netlist simulation ( ModelSim ) Application- based activity (. vcd format) Power profiling ( PrimeTime PX ) Chip’s floorplan extraction ( Cadence Temperature SoC Encounter & Perl profile conversion script ) extraction ( HotSpot )

Linear extrapolation (Matlab) IMD leakage in stress conditions ############################## Wire detailed report ############################## ################################################################################## Temperature Net: core0/leon3core0/leon3s0_1/p0/iu0/n5750 Input pin: core0/leon3core0/leon3s0_1/p0/iu0/r_reg_X__DATA__0__5_/D profile Output pin: core0/leon3core0/leon3s0_1/p0/iu0/U450/ZN Total Capacitance(pf): 0.00263318 (HotSpot) Layout extraction Total Length(um): 9.545 ------------------------------------------------------------------ (DB Access & Tcl) Wire: 0x22dcf738 Layer metal3 Direction: dbcWireE Length: 7.42 um Thickness 0.14 um Width 0.0699999999999 um Location: (1516.935, 1230.145) (1524.425, 1230.215) (Unit: um) Via: VIA23_1cut From STA ****** above ****** (Cadence ETS) Unit: um Start End Distance Wire 1524.215 1525.685 0.21 0x22e19530 1478.855 1766.765 0.35 0x229d1dbc 1473.115 1546.825 0.0700000000002 0x229c95cc ****** below ****** Unit: um Start End Distance Wire 1508.255 1519.945 0.0699999999999 0x22bc6b88 1523.515 1531.145 0.0699999999999 0x22ae4bb4 TDDB_LUT.lib 1523.375 1526.525 0.21 0x22eaa270 construction (Synopsys HSPICE ) Neighboring wires Linear interpolation ( wire.report ) (Matlab)

Length(um) Length(neighbor um) start_point(um) Leakage(uA) distance(um): Generation of S pice simulation files. Generation of S pice simulation files. delay_change_ratio 200 30 0 0 0.06 : 0 200 30 0 0.25 0.06 : 0.000819672131147554 200 30 0 0.5 0.06 : 0.000819672131147554 200 30 0 0.75 0.06 : 0.00163934426229511 Pre-overlap Overlap Post-overlap 200 30 0 1 0.06 : 0.00163934426229511 region region region 200 30 0 2.5 0.06 : 0.00409836065573777 Delay look-up library 200 30 0 5 0.06 : 0.00737704918032785 200 30 0 10 0.06 : 0.0147540983606558 200 30 0 15 0.06 : 0.0221311475409837 200 30 0 20 0.06 : 0.0295081967213116 200 30 0 25 0.06 : 0.0368852459016394 200 30 0 30 0.06 : 0.0442622950819673 200 30 0 40 0.06 : 0.059016393442623 200 30 0 50 0.06 : 0.0737704918032787 Main wire Execution of S pice simulations through batch Execution of S pice simulations through batch script. script. Case 1 Case 2 Case 3 Generation of the delay look-up library from Generation of the delay look-up library from simulation reports. simulation reports. Case 4

An AMBA-compliant LEON3-based S oC, where more LEON3 cores can be attached on the AHB controller.

� Parameterized VHDL code of the LEON3 MP-S oC system generated automatically by the Gaisler Research tools. � Ment or Graphics ModelS im, used for the post-layout functional simulation and the activity extraction. � S ynopsys Design Compiler, used for the front-end part (synthesis). � Cadence S oC Encount er, used as the place-and-route tool. � Cadence S oC Encount er Dat aBase Access commands, used for the extraction of wires from the layouts. � Perl scipt, for the floorplan conversion required from HotS pot.

CPU 1 CPU 0 The 2.32 x1.86 mm 2 floorplan of the MP-S oC, used in the presented place-and- route scenarios (in 0.9V TS MC 45nm std. cell library).

Timing-driven Congestion-driven approach (TP-NR) approach (TP-NR)

Temperat ure profile from mat rix mult iplicat ion Timing-driven st rat egies ( TP-NR & TP-TR ) yield the best layouts regarding TDDB-induced timing overhead! Critical path delay ( ps ) rise over time ( years ) due to TDDB, for the presented place-and-route scenarios.

� Wirelength is more important than distance, regarding Delay ratio. � Delay ratio increases almost linearly over time, for given temperature. Delay increment ratio of a wire vs operation time (years) and i) temperature ( left ) ii) inter-metal distance & wirelength ( right ).