Low Power Flitwise Routing in an Unidirectional Torus with Minimal - - PowerPoint PPT Presentation

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Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering J org Mische and Theo Ungerer Systems and Networking Department of Computer Science University of Augsburg NoCArc Workshop Vancouver, Canada, 2012-12-01 J org

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SLIDE 1

Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

J¨

  • rg Mische and Theo Ungerer

Systems and Networking Department of Computer Science University of Augsburg

NoCArc Workshop Vancouver, Canada, 2012-12-01

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 2

Motivation

On-chip Networks for Embedded Systems

◮ Connect small cores by a NoC ◮ Routers must be small and power-efficient, too

Alternative Router Design

◮ Reduce area and power consumption ◮ Reduce complexity of router ◮ Provide acceptable network throughput

2012-12-01 J¨

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SLIDE 3

Outline

Router Microarchitecture Routing Algorithm Evaluation of Throughput and Costs

2012-12-01 J¨

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SLIDE 4

Conventional Router in a Mesh

2012-12-01 J¨

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SLIDE 5

Conventional Router Architecture

2012-12-01 J¨

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SLIDE 6

Conventional Router Architecture

mesh

2012-12-01 J¨

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SLIDE 7

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

2012-12-01 J¨

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SLIDE 8

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

◮ 5x5 crossbar

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 9

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

◮ 5x5 crossbar

wormhole routing

2012-12-01 J¨

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SLIDE 10

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

◮ 5x5 crossbar

wormhole routing

◮ input or output buffers

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 11

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

◮ 5x5 crossbar

wormhole routing

◮ input or output buffers ◮ buffers for

virtual channels

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 12

Conventional Router Architecture

mesh

◮ 4+1 input ports,

4+1 output ports

◮ 5x5 crossbar

wormhole routing

◮ input or output buffers ◮ buffers for

virtual channels

◮ pipelined logic

2012-12-01 J¨

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SLIDE 13

Unidirectional Torus

comparision with mesh

bidirectional 1× bandwith

  • 0.5×

#ports/links + 2× link length

  • 1×

link area

  • 0.5×

link capacity

  • 2012-12-01

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SLIDE 14

Folded Unidirectional Torus

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SLIDE 15

Reducing Router Complexity

2012-12-01 J¨

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SLIDE 16

Reducing Router Complexity

unidirectional torus

2012-12-01 J¨

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SLIDE 17

Reducing Router Complexity

unidirectional torus

◮ 2+1 input ports,

2+1 output ports

2012-12-01 J¨

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SLIDE 18

Reducing Router Complexity

unidirectional torus

◮ 2+1 input ports,

2+1 output ports

◮ 3x3 crossbar

2012-12-01 J¨

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SLIDE 19

Reducing Router Complexity

unidirectional torus

◮ 2+1 input ports,

2+1 output ports

◮ 3x3 crossbar

semi-bufferless routing

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 20

Reducing Router Complexity

unidirectional torus

◮ 2+1 input ports,

2+1 output ports

◮ 3x3 crossbar

semi-bufferless routing

◮ 1 buffer

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 21

Reducing Router Complexity

unidirectional torus

◮ 2+1 input ports,

2+1 output ports

◮ 3x3 crossbar

semi-bufferless routing

◮ 1 buffer ◮ simplified routing logic

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 22

Paternoster Routing

◮ constantly rotating x-rings

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SLIDE 23

Paternoster Routing

◮ constantly rotating x-rings

2012-12-01 J¨

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SLIDE 24

Paternoster Routing

◮ constantly rotating x-rings

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 25

Paternoster Routing

◮ constantly rotating x-rings

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 26

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings

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SLIDE 27

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings

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SLIDE 28

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings

2012-12-01 J¨

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SLIDE 29

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings

2012-12-01 J¨

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SLIDE 30

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot

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SLIDE 31

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 32

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 33

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 34

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport

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SLIDE 35

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer

2012-12-01 J¨

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SLIDE 36

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 37

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 38

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot ◮ y transport

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 39

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot ◮ y transport

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 40

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot ◮ y transport

2012-12-01 J¨

  • rg Mische / Low Power Flitwise Routing in an Unidirectional Torus with Minimal Buffering

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SLIDE 41

Paternoster Routing

◮ constantly rotating x-rings ◮ constantly rotating y-rings ◮ enter x-ring if empty slot ◮ x transport ◮ turn to corner buffer ◮ enter y-ring if empty slot ◮ y transport ◮ eject

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SLIDE 42

Conflicts

Corner buffer full → extra round Conflict at local eject port → extra round No free slot → request from predecessor

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SLIDE 43

Flow Control

Single Flit Packets

◮ Enable large data chunks by preserving flit order ◮ Simplify flow control

Preserving flit order

◮ Fixed route (X-Y) ◮ Preserve order in extra rounds

Overhead

◮ Each flit carries destination → increase link width ◮ In return: save head flit

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SLIDE 44

Evaluation

◮ Main focus: comparability with other low power router

publications

◮ Baseline: conventional router with 2 buffers per input port and

2 virtual channels (VC2x2)

◮ Throughput: synthetic traffic patterns from booksim ◮ Power/area: Orion 2.0 at 65nm

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SLIDE 45

Uniform Random Traffic

0.00 0.05 0.10 0.15 0.20 0.25 0.30 20 40 60 80 100

  • ffered load [flits/cycle/node]

average latency [cycles] PN1 PN2 PN4 PN8 PN16 PN32 VC2x2

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SLIDE 46

Tornado Traffic

0.00 0.05 0.10 0.15 0.20 0.25 0.30 20 40 60 80 100

  • ffered load [flits/cycle/node]

average latency [cycles] PN1 PN2 PN4 PN8 PN16 PN32 VC2x2

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SLIDE 47

Tornado Traffic Pattern

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SLIDE 48

Neighbor Traffic Pattern

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SLIDE 49

Neighbor Traffic

0.0 0.2 0.4 0.6 0.8 1.0 20 40 60 80 100

  • ffered load [flits/cycle/node]

average latency [cycles] PN1−SW PN32−SW PN−NE VC2x2

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SLIDE 50

Area

VC2x8 VC2x4 VC2x2 VC2x1 VC1x8 VC1x4 VC1x2 VC1x1 PN64 PN32 PN16 PN8 PN4 PN2 PN1 crossbar VC allocator switch allocator buffers area [mm²] 0.00 0.02 0.04 0.06 0.08 0.10 0.12

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SLIDE 51

Power vs. Throughput

  • 0.0

0.1 0.2 0.3 0.4 10 20 30 40 50

  • PN(1,...,64)

VC1x(1,2,4) VC2x(1,2,4) VC4x(1,2,4) saturation throughput [flits/cycle/node] power [mW]

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SLIDE 52

Conclusion

Summary

◮ Semi-bufferless routing in an unidirectional torus ◮ Save energy by omitting

packets, flow control and virtual channels

◮ Low power for low throughput

Future Work

◮ Real workloads ◮ Power modelling for structural size < 65nm (DSENT / VHDL) ◮ Guaranteed Service (GS) for real-time applications

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SLIDE 53

Thank You

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