Lecture 8: Sequential Networks and Finite State Machines CSE 140: - - PowerPoint PPT Presentation

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Lecture 8: Sequential Networks and Finite State Machines CSE 140: - - PowerPoint PPT Presentation

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Lecture 8: Sequential Networks and Finite State Machines CSE 140: Components and Design Techniques for Digital Systems Spring 2014 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

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Lecture 8: Sequential Networks and Finite State Machines

CSE 140: Components and Design Techniques for Digital Systems Spring 2014

CK Cheng, Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

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Combinational

CLK CLK A B C D

Sequential Networks

  • 1. Components F-Fs
  • 2. Specification
  • 3. Implementation: Excitation Table

S(t) X Y CLK

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Specification

  • Combinational Logic

– Truth Table – Boolean Expression – Logic Diagram (No feedback loops)

  • Sequential Networks: State Diagram

(Memory)

– State Table and Excitation Table – Characteristic Expression – Logic Diagram (FFs and feedback loops)

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Specification: Finite State Machine

  • Input Output Relation
  • State Diagram (Transition of States)
  • State Table
  • Excitation Table (Truth table of FF inputs)
  • Boolean Expression
  • Logic Diagram
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Specification: Examples

  • Transition from circuit to finite state

machine representation

– Netlist => State Table => State Diagram => Input Output Relation

  • Example 1: a circuit with D Flip Flops
  • Example 2: a circuit with other Flip Flops

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Building Sequential Circuits and describing their behavior

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What we will learn:

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  • 1. Given a sequential circuit, describe its behavior over time
  • 2. Given the behavior of a sequential circuit, implement the circuit

Sequential Circuit: Wall-E How does Wall-E behave?

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What does it mean to describe the behavior of a sequential circuit

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Specify how the output of the circuit changes as a function of inputs and the state of the circuit

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PI Q: What is the difference between the state of a circuit and its output?

  • A. The output is independent of the state
  • B. The output and state are the same thing
  • C. The state is special type of output that is fed

back into the circuit

  • D. The state is input information that is

independent of previous outputs

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State: What is it? Why do we need it?

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Free running 2 bit Counter Symbol/ Circuit Behavior over time time

CLK Q0 Q1

What is the expected output of the counter over time?

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State: What is it ? Why do we need it?

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Symbol/ Circuit Behavior over time time

CLK

2 bit Counter PI Q: At time t1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t2)?

  • A. All the outputs of the counter until t1
  • B. The initial output of the counter at time t=0
  • C. The output of the counter at current time t1
  • D. We cannot determine the output of the counter at t2 prior to t2

t1 t2

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State: What is it ? Why do we need it?

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  • The state is distilled output information that tells us everything we

need to know to produce the next output. That is why it is fed back into the circuit.

  • In the case of the 2-bit counter the output (i.e. the current count) is

also the state of the counter. But we could have had other outputs that were not part of the state. E.g. A signal that indicated whether the current count is greater than 2.

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Finite State Machines: Describing circuit behavior over time

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2 bit Counter Symbol/ Circuit Diagram that depicts behavior over time

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State Diagrams: Describing circuit behavior over time

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State diagram of the 2 bit counter S0 S1 S2 S3 PI Q: What information is not explicitly indicated in the state diagram?

  • A. The input to the circuit
  • B. The output of the circuit
  • C. The time when state transitions
  • ccur
  • D. The current state of the circuit.
  • E. The next state of the circuit.

Finite State Machine

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Implementing the 2 bit counter

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00 01 10 11

State Diagram State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

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Implementing the 2 bit counter

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

PI Q: To obtain the outputs Q0(t+1) and Q1(t+1) from the inputs Q1(t) and Q0(t) we need to use:

  • A. Combinational logic
  • B. Some other logic
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Implementing the 2 bit counter

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

Q0(t) Q1(t) Q0(t+1) Q1(t+1) PI Q: What is wrong with the 2-bit counter implementation shown above

  • A. The combinational circuit is incorrect
  • B. The circuit state changes correctly but continuously rather than at the rising

edge of the clock signal

  • C. The output of the circuit is unreliable because inputs can get corrupted
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Implementing the 2 bit counter

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State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 1

We store the current state using D-flip flops so that:

  • The inputs to the combinational circuit don’t change while the

next output is being computed

  • The transition to the next state only occurs at the rising edge of the

clock

Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK Implementation of 2-bit counter

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Generalized Model of Sequential Circuits

  • 1. Components F-Fs
  • 2. Specification
  • 3. Implementation: State Table/ Excitation Table

S(t) X Y CLK

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Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t)

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Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t) Characteristic Expression: y(t) = Q0(t+1) = Q1(t+1) =

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Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t) Characteristic Expression: y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 1 1 0 1 1

PS

input

x=0 x=1

Q1(t) Q0(t) | (Q1(t+1) Q0(t+1), y(t)) Present State | Next State, Output

S0 S1 S2 S3

PS

input

x=0 x=1

Netlist ó State Table ó State Diagram ó Input Output Relation

State Assignment

Characteristic Expression: y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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State table

0 0 0 1 1 0 1 1

PS

input

x=0 x=1 01, 0 00, 0 10, 0 00, 0 11, 0 00, 0 00, 1 00, 1

Q1(t) Q0(t) | Q1(t+1) Q0(t+1), y(t) Present State | Next State, Output

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1

Let: S0 = 00 S1 = 01 S2 = 10 S3 = 11

Remake the state table using symbols instead of binary code , e.g. ’00’ Netlist ó State Table ó State Diagram ó Input Output Relation

State Assignment

y(t) = Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)’ Q0(t)’ Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))

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Netlist ó State Table ó State Diagram ó Input Output Relation Given inputs and initial state, derive output sequence

S1 S2 S3 S0

Time 1 2 3 4 5 Input 1

  • State

S0 Output

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1

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Netlist ó State Table ó State Diagram ó Input Output Relation Example: Given inputs and initial state, derive

  • utput sequence

x/y

S1 S2 S3 S0

0/0 0/0 0/0 1/0 1/0

Time 1 2 3 4 5 Input 1

  • State

S0 S1 S0 S1 S2 S3 Output 0 1

(0 or 1)/1

S0 S1 S2 S3

PS

input

x=0 x=1

S1, 0 S0, 0 S2, 0 S0, 0 S3, 0 S0, 0 S0, 1 S0, 1 1/0

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y(t) = Q1(t)Q0(t) T0(t) = x(t) Q1(t) T1(t) = x(t) + Q0(t)

X

T Q Q’ T Q Q’

y

Q0 Q1 T0 T1

Example 3 Circuit with T Flip-Flops

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Logic Diagram => Excitation Table => State Table

y(t) = Q1(t)Q0(t) T0(t) = x(t) Q1(t) T1(t) = x(t) + Q0(t) Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t) Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)

id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 1 1 1 2 1 1 1 1 3 1 1 1 1 1 4 1 1 5 1 1 1 1 1 6 1 1 1 1 1 7 1 1 1 1 1 1

Excitation Table: Truth table of the F-F inputs

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Excitation Table: iClicker

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In excitation table, the inputs of the flip flops are used to produce

  • A. The present state
  • B. The next state
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30 id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 1 1 1 2 1 1 1 1 3 1 1 1 1 1 4 1 1 5 1 1 1 1 1 6 1 1 1 1 1 7 1 1 1 1 1 1

Excitation Table =>State Table => State Diagram

PS\Input X=0 X=1 S0 S1 S2 S3 State Assignment S0 00 S1 01 S2 10 S3 11

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31 id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 1 1 1 2 1 1 1 1 3 1 1 1 1 1 4 1 1 5 1 1 1 1 1 6 1 1 1 1 1 7 1 1 1 1 1 1

Excitation Table =>State Table => State Diagram

S0 S1 S3 S2 PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S3,0 S2 S2,0 S1,0 S3 S1,1 S0,1 State Assignment S0 00 S1 01 S2 10 S3 11

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32 id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y 1 1 1 1 2 1 1 1 1 3 1 1 1 1 1 4 1 1 5 1 1 1 1 1 6 1 1 1 1 1 7 1 1 1 1 1 1

Excitation Table =>State Table => State Diagram

0/0

S0 S1 S3 S2

0/0 1/1 0/1 0, 1/0 1/0 1/0

PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S3,0 S2 S2,0 S1,0 S3 S1,1 S0,1 State Assignment S0 00 S1 01 S2 10 S3 11

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Netlist ó State Table ó State Diagram ó Input Output Relation

0/0

S0 S1 S3 S2

0/0 1/1 0/1 0, 1/0 1/0 1/0

PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S3,0 S2 S2,0 S1,0 S3 S1,0 S0,1

Time 1 2 3 4 5 Input 1 1 1

  • State

S0 Output

Example: Output sequence

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Netlist ó State Table ó State Diagram ó Input Output Relation

0/0

S0 S1 S3 S2

0/0 1/1 0/1 0, 1/0 1/0 1/0

PS\Input X=0 X=1 S0 S0,0 S2,0 S1 S3,0 S3,0 S2 S2,0 S1,0 S3 S1,0 S0,1

Time 1 2 3 4 5 Input 1 1 1

  • State

S0 S0 S2 S1 S3 S0 Output 0 1

Example: Output sequence

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Implementation

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State Diagram => State Table => Logic Diagram

  • Canonical Form: Mealy and Moore Machines
  • Excitation Table
  • Truth Table of the F-F Inputs
  • Boolean algebra, K-maps for combinational

logic

  • Examples
  • Timing
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Canonical Form: Mealy and Moore Machines

Combinational Logic

x(t) y(t) CLK

C2 C1

y(t) CLK x(t)

C1 C2

CLK x(t) y(t)

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Mealy Machine: yi(t) = fi(X(t), S(t)) Moore Machine: yi(t) = fi(S(t)) si(t+1) = gi(X(t), S(t)) C1 C2

CLK x(t) y(t)

Mealy Machine C1 C2

CLK x(t) y(t)

Moore Machine

S(t) S(t)

Canonical Form: Mealy and Moore Machines

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Implementation: State Diagram => State Table => Netlist

Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.

S1 S0

a/0 b/0 a/0 b/1

S2

a/0 b/0

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State Diagram => State Table with State Assignment

State Assignment S0: 00 S1: 01 S2: 10

PS\x a b S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1 PS\x 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1

Q1(t+1)Q0(t+1), y a: 0 b: 1

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Example 2: State Diagram => State Table => Excitation Table => Netlist PS\x 0 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1

id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 00 4 100 10 5 101 00 1 6 110

  • 7

111

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0 2 6 4 1 3 7 5

x(t) Q1

0 1 - 1 0 0 - 0

Q0

D1(t): D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x id Q1Q0x D1D0 y 000 01 1 001 00 2 010 10 3 011 00 4 100 10 5 101 00 1 6 110

  • 7

111

  • Example 2: State Diagram => State Table

=> Excitation Table => Netlist

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D Q Q’ D Q Q’

Q1 Q0 D1 D0 Q0 Q1 x’ D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x x y Q’1 Q’0 x’ Example 2: State Diagram => State Table => Excitation Table => Netlist

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D Q Q’ D Q Q’

Q1 Q0 D1 D0 Q0 Q1 x’ x y Q’1 Q’0 x’

Example 3: State Diagram => State Table => Excitation Table => Netlist S1 S0

a/0 b/0 a/0 b/1

S2

a/0 b/0

iClicker: The relation between the above state diagram and sequential circuit.

  • A. One to one.
  • B. One to many
  • C. Many to one
  • D. Many to many

E. None of the above

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Finite State Machine Example

  • Traffic light controller

– Traffic sensors: TA, TB (TRUE when there’s traffic) – Lights: LA, LB

TA LA TA LB TB TB LA LB

Academic Ave. Bravado Blvd. Dorms Fields Dining Hall Labs

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FSM Black Box

  • Inputs: CLK, Reset, TA, TB
  • Outputs: LA, LB

TA TB LA LB CLK Reset Traffic Light Controller

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FSM State Transition Diagram

  • Moore FSM: outputs labeled in each state
  • States: Circles
  • Transitions: Arcs

S0 LA: green LB: red Reset

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FSM State Transition Diagram

  • Moore FSM: outputs labeled in each state
  • States: Circles
  • Transitions: Arcs

S0 LA: green LB: red S1 LA: yellow LB: red S3 LA: red LB: yellow S2 LA: red LB: green TA TA TB TB Reset

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FSM State Transition Table

PS Inputs NS TA TB S0 X S1 S0 1 X S0 S1 X X S2 S2 X S3 S2 X 1 S2 S3 X X S0

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State Transition Table

PS Inputs NS Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1) X 1 1 X 1 X X 1 1 X 1 1 1 X 1 1 1 1 X X

State Encoding S0 00 S1 01 S2 10 S3 11

Q1(t+1)= Q1(t)Å Q0(t) Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B

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FSM Output Table

PS Outputs Q1 Q0 LA1 LA0 LB1 LB0 1 1 1 1 1 1 1 1 1 1

Output Encoding green 00 yellow 01 red 10

LA1 = Q1 LA0 = Q’1Q0 LB1 = Q’1 LB0 = Q1Q0

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FSM Schematic: State Register

S1 S0 S'1 S'0 CLK

state register

Reset r

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Logic Diagram

S1 S0 S'1 S'0 CLK

next state logic state register

Reset TA TB

inputs

S1 S0 r

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FSM Schematic: Output Logic

S1 S0 S'1 S'0 CLK

next state logic

  • utput logic

state register

Reset LA1 LB1 LB0 LA0 TA TB

inputs

  • utputs

S1 S0 r