Lecture 6: Universal Gates CSE 140: Components and Design Techniques - - PowerPoint PPT Presentation

Lecture 6: Universal Gates

CSE 140: Components and Design Techniques for Digital Systems Spring 2014

CK Cheng, Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

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Combinational Logic: Other Types of Gates

§ Universal Set of Gates § Other Types of Gates 1) XOR 2) NAND / NOR 3) Block Diagram Transfers: Converting a circuit to an equivalent circuit

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Universal Set

Universal Set: A set of gates such that every switching

function can be implemented with gates in this set. Ex: {AND, OR, NOT} {AND, NOT} {OR, NOT}

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Universal Set

Universal Set: A set of gates such that every Boolean

function can be implemented with gates in this set. Ex: {AND, OR, NOT} {AND, NOT} OR can be implemented with AND & NOT gates a+b = (a’b’)’ {OR, NOT} AND can be implemented with OR & NOT gates ab = (a’+b’)’ {XOR} is not universal {XOR, AND} is universal

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iClicker

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Is the set {AND, OR} (but no NOT gate) universal?

• A. Yes
• B. No

Universal Set

{AND, NOT} combined into a single gate: {OR, NOT} combined into into a single gate:

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• 1. Implementing NOT using NAND
• 2. Implementing AND using NAND
• 3. Implementing OR using NAND

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Implementing NOT, AND and OR using NAND gates

• 1. Implementing NOT using NOR
• 2. Implementing OR using NOR
• 3. Implementing AND using NOR

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Implementing NOT, AND and OR using NOR gates

• 1. Implementing NOT using XOR

X 1 = X.1’ + X’.1 = X’ if constant “1” is available.

• 2. Implementing OR using XOR and AND

Same as implementing OR using AND and NOT except NOT is implemented using XOR as shown above

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Universal gates {XOR, AND} 1

Universal Set

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Remark: Universal set is a powerful concept to identify the coverage of a set of gates afforded by a given technology.

Other Types of Gates

(a) Commutative X Y = Y X (b) Associative (X Y) Z = X (Y Z) (c) 1 X = X’ 0 X = 0X’ + 0’X = X (d) X X = 0, X X’ = 1 1) XOR X Y = XY’ + X’Y

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X Y XY’ X’Y

e) if ab = 0 then a b = a + b Proof: If ab = 0 then a = a (b+b’) = ab+ab’ = ab’ b = b (a + a’) = ba + ba’ = a’b a+b = ab’ + a’b = a b f) X XY’ X’Y (X + Y) X = ?? To answer, we apply Shannon’s Expansion.

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Shannon’s Expansion (for switching functions)

Formula: f (x,Y) = x * f (1, Y) + x’ * f (0, Y) Proof by enumeration: If x = 1, f (x,Y) = f (1, Y) : 1*f (1, Y) + 1’*f(0,Y) = f (1, Y) If x = 0, f(x,Y) = f (0, Y) : 0*f (1, Y) + 0’*f(0,Y) = f(0, Y)

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Back to our problem…

X XY’ X’Y (X + Y) X = ? Þ X (XY’) (X’Y) (X + Y) X = f (X, Y) If X = 1, f (1, Y) = 1 Y’ 0 1 1 = Y If X = 0, f (0, Y) = 0 0 Y Y 0 = 0 Thus, f (X, Y) = XY

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XOR gates

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iClicker: a+(b c) = (a+b) (a+c) ?

• A. Yes
• B. No

2) NAND, NOR gates NAND, NOR gates are not associative

Let a | b = (ab)’ (a | b) | c ≠ a | (b | c)

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3) Block Diagram Transformation a) Reduce # of inputs. ó ó

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• b. DeMorgan’s Law

ó (a+b)’ = a’b’ ó (ab)’ = a’+b’

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• c. Sum of Products (Using only NAND gates)

ó ó Sum of Products (Using only NOR gates) ó ó

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• d. Product of Sums (NOR gates only)

ó ó

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NAND, NOR gates

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Remark: Two level NAND gates: Sum of Products Two level NOR gates: Product of Sums

Part II. Sequential Networks

Memory / Timesteps Clock

Flip flops Specification Implementation

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Reading

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[Harris] Chapter 3, 3.1, 3.2