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Lecture 3: Model-checker NuSMV B. Srivathsan Chennai Mathematical - PowerPoint PPT Presentation

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Lecture 3: Model-checker NuSMV B. Srivathsan Chennai Mathematical Institute NPTEL-course July - November 2015 1 / 31 Model-checker Specify the model of the system Specify the requirements Model-checker will automatically check if system

  1. � × × request=0 request=1 request=0 G (request=0) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS does not satisfy G (request=0) request=1 request=0 request=0 busy ready ready . . . . . . . . . 13 / 31

  2. Execution satisfies G (expr) if expr evaluates to T in all its states ... T T T T T T 14 / 31

  3. Execution satisfies G (expr) if expr evaluates to T in all its states ... T T T T T T Transition system satisfies G (expr) if all its executions satisfy G (expr) 14 / 31

  4. Checking the G requirement: NuSMV demo 15 / 31

  5. Requirement type 2: F 16 / 31

  6. Requirement type 2: F l 1 , x=0 F ( x >= 5 ) l 1 l 2 , x=0 l 1 , x=1 x := x+1 x < 10 l 2 l 2 , x=1 . . . l 1 , x=9 l 2 , x=9 l 1 , x=10 16 / 31

  7. Requirement type 2: F l 1 , x=0 F ( x >= 5 ) l 1 l 2 , x=0 l 1 , x=1 x := x+1 x < 10 l 2 l 2 , x=1 . . . TS of above PG with initial value x=0 satisfies F ( x >= 5 ) l 1 , x=9 l 2 , x=9 l 1 , x=10 16 / 31

  8. request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  9. � request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  10. � � request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  11. � � × request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  12. � � × request=0 request=1 request=0 F (request=1) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 ... request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS does not satisfy F (request=1) request=1 request=0 request=0 busy ready ready . . . . . . . . . 17 / 31

  13. Execution satisfies F (expr) if expr evaluates to T in one of its states ... T 18 / 31

  14. Execution satisfies F (expr) if expr evaluates to T in one of its states ... T Transition system satisfies F (expr) if all its executions satisfy F (expr) 18 / 31

  15. Checking the F requirement: NuSMV demo 19 / 31

  16. Coming next: Combining G and F 20 / 31

  17. request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  18. � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  19. � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  20. � � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  21. � � � request=0 request=1 request=0 G ( request=1 => F status=busy ) ready ready ready request=1 request=1 ready busy request=0 request=1 request=0 busy busy ready request=0 request=0 request=0 request=0 request=0 ready busy ready ready ready request=1 request=1 request=0 busy busy ready TS satisfies G ( request => F (status=busy) ) request=1 request=0 request=0 busy ready ready . . . . . . . . . 21 / 31

  22. Summary Using NuSMV Format for writing models G and F requirements 22 / 31

  23. Summary Using NuSMV Format for writing models G and F requirements Coming next: More circuits 22 / 31

  24. in 1 NAND out in 2 23 / 31

  25. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; DEFINE −− ZERO DELAY out := !(in1 & in2); 23 / 31

  26. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  27. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  28. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; 0 0 0 1 DEFINE 1 1 −− ZERO DELAY out := !(in1 & in2); 1 1 0 1 1 0 23 / 31

  29. in 1 NAND out in 2 MODULE main VAR in1: boolean; in2: boolean; out: boolean; ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 24 / 31

  30. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  31. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  32. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  33. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  34. in 1 NAND out in 2 MODULE main VAR 0 0 in1: boolean; 0 0 0 1 in2: boolean; out: boolean; 0 0 ASSIGN 1 1 0 1 −− UNIT DELAY init(out) := TRUE; 1 1 next(out) := !(in1 & in2); 0 0 0 1 1 1 1 1 0 1 24 / 31

  35. in 1 NAND out MODULE main in 2 VAR input1: boolean; input2: boolean; 0 0 q: nand2(input1, input2); 0 0 0 1 MODULE nand2(in1, in2) 0 0 VAR 1 1 0 1 out: boolean; ASSIGN 1 1 −− UNIT DELAY 0 0 0 1 init(out) := TRUE; next(out) := !(in1 & in2); 1 1 1 1 0 1 25 / 31

  36. MODULE main VAR x1: boolean; x2:boolean; y1: boolean; y2:boolean; q1: nand2(x1, x2); x 1 q2: nand2(y1, y2); NAND x 2 DEFINE XOR −− ZERO DELAY fout := q1.out xor q2.out; y 1 NAND y 2 MODULE nand2(in1, in2) VAR out: boolean; ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 26 / 31

  37. MODULE main VAR x: boolean; y: boolean; q1: nand2(x, q2.out); x q2: nand2(q1.out, y); NAND DEFINE XOR −− ZERO DELAY fout := q1.out xor q2.out; NAND y MODULE nand2(in1, in2) VAR out: boolean ASSIGN −− UNIT DELAY init(out) := TRUE; next(out) := !(in1 & in2); 27 / 31

  38. Coming next: Three-bit adder 28 / 31

  39. MODULE counter_cell(carry_in) VAR value:boolean; ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  40. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR value:boolean; ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  41. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR value:boolean; 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  42. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  43. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  44. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 value:boolean; 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  45. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 1 value:boolean; 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  46. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 1 1 value:boolean; 0 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  47. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN init(value):=FALSE; next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  48. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN init(value):=FALSE; 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  49. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  50. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  51. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 1 init(value):=FALSE; 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  52. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 1 init(value):=FALSE; 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  53. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 1 init(value):=FALSE; 0 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  54. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 0 1 init(value):=FALSE; 0 0 0 1 0 0 next(value):= value xor carry_in; DEFINE carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

  55. bit2 bit1 bit0 carry_in 0 0 1 MODULE counter_cell(carry_in) value 0 0 0 0 0 0 carry_out VAR 0 1 1 value:boolean; 0 0 0 0 1 1 ASSIGN 0 0 1 init(value):=FALSE; 0 0 0 1 0 0 next(value):= value xor carry_in; 1 1 1 DEFINE 0 0 1 1 1 1 carry_out := carry_in & value; MODULE main VAR bit0:counter_cell(TRUE); bit1:counter_cell(bit0.carry_out); bit2:counter_cell(bit1.carry_out); 29 / 31

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