LDO application and design requirements Carlo.Fiocchi - AMS Italy - - PowerPoint PPT Presentation

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LDO application and design requirements

Carlo.Fiocchi - AMS Italy CAS Workshop 2017 Almo Collegio Borromeo - Pavia 21 March 2017

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Introduction

LDO design is quite, I would say extremely, specific. May be none of the attendee will consider this topic in the future. Nevertheless it is possible to make fruitful a discuss on it, even in the very short duration of this lesson It is not a matter to show in details any design aspect and how the solutions are effectively implemented The matter is so wide, so many proposed solutions are found in literature, that this cannot be solved in 1 hour and half. Moreover such a lesson, for those not fully concerned, would result boring soon. On the contrary, we can take a great advantage from LDO critical design challenges: this kind circuit has an intrinsic weakness in stability, usually the hot topic of any conference, lesson and paper. The poor safety margin affecting stability is the cause of frequent particular problems. They look quite surprising indeed, like

• AC bode diagram with 90deg PM and incapable to predict the instability shown by a transient simulation
• extremely large noise of an amplifier, much larger than the expected result.
• an AC supply disturbance might cause an error in a High resolution ADC converter for DC signals

Only an interpretation which is at the same time original and strict would allow a clear view to solve these problems and go ahead. Reporting these interpretations, and the associated achievements, is interesting by itself: they cannot be found in paper, lessons but they are useful to open anyone’s mind At the same time they can be exploited in other design activities, even totally different from LDO applications: even if usually the safety margins for stability are superior and prevent the encountered problems to be triggered, the same might pop up if trying to

• utperforming what is at the state of the art. If not understood and solved, solutions advantageous from a theorical point of view

should be abandoned to choose simpler but surely less performing ones Hence, these kind of learnt lessons from LDO design challenge has an inestimable value. So let’s take the opportunity offered by today conference

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A voltage source satisfying the following requirements:

• Low drop regulation

small voltage between voltage supply and regulated voltage

• Accuracy
• Large current sourcing capability

its output acts as a supply for a load

• Capability to sustain large capacitors at the load
• PSRR
• Provide a clean, ripple-free and noise-reduced, regulated voltage

Basic LDO specs

Vin Vreg LDO

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The above mentioned requirements bring to a well defined architecture

• utput transistor is a PMOS device:

Vds copes low drop needs better than NMOS Vgs allow large swing at PMOS gate: ensures large drive capability even in triode conditions amplification stage after a virtual ground: Minimizes output voltage variations after load changes continuous time system: no ripple is a key feature, unlike switching converters. No clock.

LDO Architecture

Vin R1 R2 A Vref

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Specification for each building block Amplifier stage: rail to rail output swing moderately high gain A PMOS device: Large size if in triode, must be capable to sustain the maximum load current with few tenths mV drop Load capacitor interaction with internal nodes for stability concerns: dominant pole determination

LDO Architecture

Vin R1 R2 A Vref Cload

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Why an LDO?

A) it splits power management sources to avoid interaction of noisy parts B) Concerns about HV supply voltage: area and CMOS circuitry implementation C) Filtering supply noise

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Why an LDO?

power management source splitting to avoid interaction of noisy parts In case Iload2 has large and frequent transient variations, Vreg1 is not disturbed by them Frequently adopted in mixed signal applications Vreg1 and Vreg2 might also be different, to have a degree of freedom for analog section dynamic range and better dissipation for the digital side

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Vreg1

Vin

R2 G1

Vref

R1

Mpout Iload Vreg2

Vin

R3 G1 R4

Mpout Iload2

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Why an LDO?

Concerns about HV supply voltage: area and CMOS circuitry implementation

• A CMOS gate cannot usually sustain more

than few Volts voltage (say from 1.8V to 5V), largely less than a battery supply (around 42V). Scaling down supply is mandatory

• A CMOS circuit for HV robustness need

area consuming protections and the minimum width does not go below some µm:

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PMOS HV vs. LV NMOS HV vs. LV

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Filtering supply noise an LDO is just a bit more sophisticated opamp. Hence its PSRR, if optimized, can be used to suppress supply noise Any variation at the supply is corrected by the feedback loop at the gate of the output transistor and only a small error affects the error amplifier input thanks to the amplifier stage A. As a result the regulated output is affected by a remarkably attenuated version of the error on the supply line

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Vin R1 R2 A Vref Cload

Why an LDO?

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Why an LDO instead of possible alternatives?

DC-DC switching regulator vs. LDO

DCDC switching converter LDO regulator Vin R1 R2 A Vref Cload

I controller Vref

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DC-DC switching regulator vs. LDO

LDO implementation An output transistor (either N or P-type) inside a feedback loop drives the

• utput current. An error amplifier and a voltage divider complete the

feedback regulation by comparing the target output to the real one and drive the gate of the output transistor.

Vref R1 R2 Erramp power transistor

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DC-DC switching regulator vs. LDO

DCDC implementation A controller senses the load voltage and eventually current: duty cycle of the clocked signal that drives the output digital driver is consequently set. A cascaded LC circuit filters out the average value and provides the regulated voltage Vout to the load

I controller Vref

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DC-DC switching regulator vs. LDO

Efficiency performance

• The LDO dissipates in the output stage :

P_diss = Iload*(Vin-Vout)

• The switching regulator dissipation depends on the
• utput transistors on-resistance Ron. Hence:

P_diss = Ron * Iload

2

=> A DCDC regulator has key advantage vs. LDO

• nce Ron*Iload << (Vin-Vout)
• LDO requires much less bias current:

=> A winning feature for light loads Vin Vout Iload

I Vsw Vout Vdd Vdd GND Vsw Vout

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DC-DC switching regulator vs. LDO

DC-DC switching regulator outperforms LDO:

• switching regulator for step up has no LDO counterpart
• better efficiency at high load current
• better efficiency at high (Vin - Vout) drops

LDO outperforms DC-DC switching regulator

• less external components
• better efficiency at low currents and low Vin-Vout
• less noisy: no ripple affects the regulated voltage
• smaller pin count (commercial devices having 3 pins only)

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LDO applications

Where to use an LDO? Take into account two contraddictory features: 1) Poor efficiency vs switching converters: large values for (VIN-VOUT) and load current are detrimental. 2) LDO analog performances largely outperform DCDC switching regulators’. => A very popular solution is to combine LDOs with DCDC converters

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LDO applications

LDO cascaded to DCDC converter: Remarkable: to suppress switching noise, avoid LDO GBW near DCDC clock where PSRR is usually at the worst value and peaking might occur

Vref R1 R2 LDO driver

DCDC switching Vin Vsys

coil

Vout both positive features combined: Trade off on efficiency: the largest portion of (Vin – Vout) is sustained by the DCD switching regulator. LDO operates with limited voltage room, set by the intermediate supply Vsys.

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LDO key parameters

Dropout It refers to the minimum supply voltage that ensures Vreg accurate enough definition: dropout as (Vin - Vout ) value when Vout drops 100mV (or a TBD % of Vout_nominal) under a decrease in Vin

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LDO key parameters

• Dropout
• key parameter for prolonged battery life
• specified at different load currents
• specified at different Vout variants: be careful

equivalent circuit:

• large input error brings PMOS gate at GND, open loop

condition

• Vdropout = Vds = ron *Iload
• ron = k/(Vgs-Vth) = k/(Vin-Vth)

Larger output transistor improves dropout value (but not recommended to save area) Other drawbacks are associated to bigger device (more parasitics) => Dropout sets the output transistor size.

Vin R1 R2 A Vref Cload

Iload Mpout Vreg

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ACCURACY

It is the combination of many contributes

• precision in the reference voltage Vref, usually a trimmed bandgap
• Offset of the LDO input stage and feedback resistor matching

not a major concern as soon as Vref trimming takes this error too into account.

• Variation in the supply voltage (line regulation)
• Variation in the load current

Among the above listed contributes, only the ones that depend on operating conditions are troublesome, while the others are corrected by trimming. Temperature drift is a minor error once a bandgap is used (worst case 80-100ppm/C° i.e. 1% in 100/125 degrees variation)

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ACCURACY

Line regulation: as soon as supply Vdd changes, the PMOS power transistor gate would adjust its gate voltage of an amount ΔVdd/gm*rds Divided by the gain A of the error amplifier, we calculate the error at the LDO virtual ground supposing Vdd variation up to 2V in a LowVoltage application gm*rds is usually larger than 10 even at the largest load current (worst case) if A=100, the virtual ground error becomes 2mV only, less than the trimming accuracy ( i.e. LSB) of the reference voltage Vref and equal to 0.17% accuracy if a bandgap is used. The higher the reference value is, the more accurate performance is achieved

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Vreg1

R2 A

Vref

R1

Mpout Iload

DVdd DVdd gm*rds

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ACCURACY

Load regulation: as soon as Iload changes, Vgs power transistor gate varies accordingly The largest value of W/L requires the smallest Vgs variation. Anyhow this is not a good design approach as area and parastics would tend to increase excessively As a rule of thumb we might expect a Vgs variation in the order of 1V to accommodate the entire load current range. For a gain A=100 this would lead to 0.8% accuracy once Vref is set by a bandgap voltage Load regulation looks the most critical issue that affects stability. Gain A should be as large as possible as well as output power transistor W/L.

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Vreg1

R2 A

Vref

R1

Mpout Iload

gm DIload DIload A*gm DIload A*gm DIload

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Output capacitor load

A large cap at the regulated output is expected as it cleans the generated voltage from noisy contributors. A key point is the impact on the stability two different approaches

• Cload exploited as compensating cap
• Cload as responsible of higher order pole of the loop.

If the first option is chosen a larger cap is always welcome as a twofold benefit

• improved stability
• cleaner regulated voltage

the second approach lends itself to a Miller compensation approach that improves accuracy thanks of the larger number of gain nodes

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Suppose by now a dominant pole at the output GBW = A*gmout/Cload Large values for A and W/L for MPOUT would imply a large value for GBW and critical stability issues are expected. Trade off between stability and accuracy as a key design challenge for an LDO

LDO stability

Vin R1 R2 A Vref Cload Mpout

Gain freq A

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PSRR

• pen loop transfer function:

simply a low pass filter: Mpout_rds and Cload. => Keep loop gain as large as possible to ensure good PSRR at any frequency When loop gain drops below unity, no voltage adjustment at Mpout gate is possible and PSRR is the one set by the open loop A large Cload looks extremely helpful for the PSRR target

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Vin Vreg rds Cload Iload 0 dB freq

gain loop LDO

• 1

Vreg to Vin from function transfer loop

• pen

= PSRR

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PSRR

Often large overshooting is observed at the crossover point between closed loop and open loop rejection. It might be dangerous especially in case the LDO is supplied by a DCDC converter clocked around the same frequency 0dB 0dB

Gloop(s) PSRR Open loop freq freq PSRR Open loop

PM

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PSRR

Why the peaking at the crossover point? Well, a very intuitive interpretation is of large help and can be used in many other design tasks, not only those referring to an LDO only. As soon as Vdd varies, the adjustment at the PMOS gate is gm*rds times less. This relationship usually holds up to some MHz Once divided by the gain of the error amplifier A, it results as an input referred error This error will be reported to the LDO output via the closed loop transfer function (Vref to Vreg) of the LDO itself.

Vreg1

R2 A

Vref

R1

Mpout Iload

DVdd DVdd gm*rds

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PSRR

0,5 1 1,5 2 2,5

• 2,5
• 2
• 1,5
• 1
• 0,5

0,5 1 0,7 1 1,5 2

Input to output transfer function: Moving towards worse phase margin values, a peaking in the input to output transfer function occurs and any error at the virtual ground is significantly amplified Improve phase margin as a key issue!

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PSRR

0,5 1 1,5 2 2,5

• 2,5
• 2
• 1,5
• 1
• 0,5

0,5 1 0,7 1 1,5 2

Did anyone think that this would not apply elsewhere, for instance in noise evaluation in a spectrum that comprises an opamp GBW? LDO usually does not achieve large phase margin and easily triggers such a problem but the above assumptions are of general validity and it is welcome to have them always in mind

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What an LDO should do too

The following specifications are requested only in particular cases: a) Overshooting suppression b) Startup inrush current control c) EMC tolerance d) Removal of the supply cap

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In general it is costly to be compliant to these requests: large area can be taken and performance get poorer. For sure the design effort increases significantly because the final achievement is often the result of a very cumbersome job It is very welcome from the designer to evaluate and eventually discuss with the customer if they can be neglected or not in the design implementation

What an LDO should do too

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Overshooting suppression an LDO might be affected by a remarkable

• vershooting at startup.

Even if not nice, this is tolerable in some cases: duration is quite limited, takes place only when the LDO is turned on and it might stay in the load reliability limits In addition, it is often observed that the overshoot can be dangerous only depending on the final steady state. In case A) the overshoot stays lower than the equilibrium value of Vreg, unlike B) which might be critical

Vref Vreg A) B)

What an LDO should do too

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Overshoot suppression

What to do? The figure shows that applying the reference with a ramp is not enough Still being based upon intuitive assumptions, it would also make sense to reduce the speed of the LDO. To avoid performance weaknesses, this can be accomplished at startup only, by selectively turning on sections of the LDO and adding filters to smoothen the bias current profile It is clear that this makes a big waste of area: It is a matter to implement, in more current branches, filters in the order of some tenths usec.

Vref Vreg A) B)

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Overshoot suppression

This approach is very cumbersome it is a matter to find the good balance to slowly turn on the power PMOS (where a very small bias current is welcome) and to turn it off rapidly when the overshoot takes place. This evident contradiction suggests us that the final outcome would be just a trade-

• ff, nothing better.

The resulting design effort would be huge, being performance sensitive to

• process parameters
• supply ramping time
• Cload and Iload values

and increases in complexity in case the LDO structure is more complex than the basic one.

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Overshoot suppression

A better approach and a general recommendation for the designer’s everyday (working, of course…J) life: Once a serious problem is encountered, a mitigation via an intuitive view is always possible: for instance once we face a too fast response, like in this case, or we notice large disturbances, the addition of filters is always of help. Anyhow the final achievement is rarely fully satisfactory: we obtain just a mitigation

• f the problem, not the elimination, and the effort spent in area, design time, may

be relevant. In these cases it is always suggested to investigate the real root of the problem. Once identified, an architecture change might solve the problem definitively and, very worth to note, the required change may be very simple.

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Overshoot suppression

the overshoot comes because the LDO starts

• nly when the input ramp crosses an NMOS

threshold. Hence a large overdrive (the feedback input is still at GND) pulls the PMOS gate down as strong as possible and for all the time it takes to Vreg to reach Vin. In this way, the current from the PMOS gets extremely large and decreases only when Vreg reaches Vin. Anyhow the output voltage will continue to rise for a long time more, until the PMOS current drops below Iload.

This is the case and let us investigate the root of the problem:

Vthn IN Vreg i1 Iload Vreg IN i1

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Overshoot suppression

The above observation is applied in a very original way By Carbonini and Draghi in Low-dropout regulator and method for voltage regulation: US 9395732 B2 Simply pre-charging the feedback cap at one NMOS threshold, the gap between the inputs is immediately closed as soon as the output PMOS is turned on to make Vreg rise after Vin crosses the NMOS threshold. No large current is accumulated into the power device and overshoot does not take place . The price to be paid is just the addition of two NMOS and one current generator, nothing else, and they automatically turn off after startup This is one of the best example to show that it is often better to investigate the root cause of the problem before putting intuitive patches. It comes a simpler, often cost free, easily portable solution that totally eliminates the problem

IN OUT +

• C

R

t = RC

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Inrush current control

Startup inrush current control when the LDO is turned on, a large current is observed at its input terminal, up to few Amps. Also its derivative is very large. Depending on the supply output impedance Z, some drop and ringing can be observed that might disturb the other circuits sharing the same supply of the LDO In general, an overshooting problem is directly associated to a large inrush current. Any solution to reduce overshoot is helpful to contrast the inrush current issue But it may be not sufficient: The overshoot solution compares voltages at the LDO input, not currents. If Cload is made large, for the same voltage we have bigger currents! if necessary, some selective filtering on the bias paths can be adopted to minimize it, causing a cumbersome design effort

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Inrush current control

As an alternative one might implement the current limiter as a series generator to the power PMOS This is the most effective solution but, unfortunately, it is extremely costly in terms of area for the same dropout value we need two PMOS having twice the size of the original solution.

Vreg1

R2 A

Vref

R1

Mpout Iload I_lim

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EMC tolerance

An EMC event is a strong coupling (up to few V) of an high frequency (100MHz and more) disturbance onto a supply pad. Typical of automotive environment It is required that the circuit still properly operates even if some degradation of the performance can be usually tolerated nothing else than a large signal PSRR issue but, being large signal related, it might trigger critical non-linearities. It is good to be familiar with this topic as it allows to make experience and bring them to other application

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EMC tolerance

An example:

An LDO was driven at the reference pin by a mux between two values Under an EMC event we could observe around 5mV DC drift at the regulated output reason why: the disturbance injects, through the input parasitic Cgd, a current id into the switch. At the same time, the overdrive

• f the switch tracks the EMC disturbance

rsw Vref M1 Cgd id LDO input

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EMC tolerance

as a result the drop across the switch is given by ron*id. Being both sinusoidally

modulated, the product generates an unexpected DC component, cause of the

• bserved DC shift at the regulator output

sin ωt * sin ωt = 0,5 * (1 + sin 2ωt)

Consideration: the error is small but it comes from a non linearity. Hence a simple AC analyses would not evidence it. If we think of an high resolution ADC converter under a possible PSRR disturbance, is it possible that the presence of multiplexing switches at its input would trigger a similar concern and might cause an error conversion?

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Removal of the supply cap

Often the supply line is exploited to transmit data. This is the case of the PSI5 protocol in automotive application but also in the consumer market similar standards are getting popular Of course a large cap on the supply does not comply with these requirements Moreover a cap occupies place on a board and removing it can be advantageous. For an LDO this makes a major challenge as an oscillation might occur

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Consider the equivalent circuit on the left and compare it to the Xtal oscillator model on the right. As soon as the supply has a relevant inductive component we are in a very similar condition Given Im(s) and Re(s) the imaginary and real part of each admittance Y=1/Z, the criteria for

• scillation in a XTAL

ImYsupply(s) + ImYin_LDO(s) = 0 ReYsupply(s) + ReYin_LDO(s) < 0

proves to be a correct tool to verify the LDO robustness against oscillation a large supply cap makes the first relationship unfeasible and prevents oscillation LDO Vbatt Zsupply(s) Zin_LDO

Zm(s) Zc(s)

resonator amplifier

Removal of the supply cap

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Unfortunately it is somewhat complicated to reach the stability target if it is not met, being difficult to understand how the input impedance of the LDO is determined An example: an LDO is designed with a NMOS output stage (there was no dropout big concern) Focus on the term Cgd, which is pretty large as the device is HV: for a NMOS level shift in the amplifier output, α=1 and Cgd does not contribute to Zin for a PMOS level shift in the amplifier output, α=0 and Cgd directly contributes to Zin value If the erramp output is a pullup current mirror whose gain is K, Cgd makes a negative contribute -Cgd/K

Vdd Cgd Iload is a*is (1- a)*is i_in

Removal of the supply cap

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This is for an LDO, but are we sure that no other components, like power operational amplifiers, would not suffer from the same problem once the capacitor at the supply is removed?

Removal of the supply cap

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What must be taken into account for project success

Design does not only mean optimal W/L and Ibias choice but also to minimize problem in the following phases of the design flow For instance Testing:

• Test time
• Test Reliability: low current correlation test

Packaging: Drop across PAD and bond-wire

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Testing

Max load current test: it measures a current above 100mA Concern: test needles undergo severe oxidation problems

• Need to clean the needles up very frequently (once every

50.000/100.000 pieces)

• Feasible?
• Suppose 100 million pieces/year production.
• Each piece takes 300msec test
• 3 samples/sec, 180 samples/minute, 10800 sample/hour, 260000 per

day => Up to 3-5 times per day clean up

• One machine working all the year for this component. Besides costs,

no stop allowed for maintenance.

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= > Reduced current test and device correlation Conceptual solution: The current in the load is mirrored by Mlim and sent to a current comparator. Increasing N times Mlim size reduces N times the max current in the load and solves the reliability concern Need to correlate low and high current test: statistic for N factor required Vin

R1 R2 A

Vref

Ilim Mlim Vreg Curr_lim Mpout Iload

Testing

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What must be taken into account for project success

• Packaging issues

Voltage Drop across PAD and bondwire. A Bond-wire has nearly 100mΩ impedance and it is in series to the LDO. Under 100mA current this makes 10mV drop, not negligible in the accuracy targets

Vreg

R2 A1

Vref

R1 Iload DVL

pad

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What must be taken into account for project success

• Packaging issues

2 internal pads, one pin on the lead-frame, two bond-wires The output pin Vreg is now in series to R2 with negligible current flow in the associated bond-wire: Vreg= (1+R2/R1)*Vref regardless the drop ΔVL Just a few mV degradation in Mpout Vds, while accuracy is guaranteed

Vreg

R2 A1

Vref

R1 Iload DVL

pad1 pad2 Mpout

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• two moderately high impedance nodes
• The same nodes loaded by remarkable

capacitance values => Both candidates to play dominant pole role. PMOS gate:

• It is a gain node, hence its impedance is large. Loaded by a large cap Cp due to

the power PMOS Cgs. OUTPUT:

• extremely large capacitor, usually 1uF. Largely varying impedance: from few

Ohms to R1+R2 => large cut off frequency variation expected

LDO stability

Vin R1 R2 A Vref Cload

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A very preliminary investigation must be carried out to verify possible reasons to make dominant one of the two poles PMOS gate cut off frequency evaluation: Suppose a realistic value for A gain = 50 If Itail=20uA => 1/gm = 4K, rout=200K Cp=100pF at least, if not more 8 KHz estimated cut off

LDO stability: evaluation of the two poles

Vin R1 R2 A Vref

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OUTPUT cut off frequency:

• large capacitor, more than hundreds nF, usually 1uF.
• Large spread in the output impedance:

i) 100mA load makes few tenths Ohm as load impedance ii) no Load condition makes R1+R2 loading 10 Ω load and 680nF makes 24KHz cut off 1MΩ load and 2.2uF makes 0.01 Hz cut off Frustrating investigation. No clear reasons found

LDO stability: evaluation of the two poles

Vin R1 R2 A Vref

8 KHz From 0.01Hz up to 24KHz

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As it is not possible to clearly state which pole can be dominant, we should try both the alternative approaches a) Vreg as dominant pole: At low and moderate loads the output is clearly dominant. Make this choice and try to push Pout gate pole at higher frequency. b) Error amplifier output as dominant: Exploiting Miller effect, pole splitting will advantageously shift the second pole at Vreg towards higher frequency

LDO stability

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Two main difficulties: a) The pole at Mpout gate is at few KHz frequency b) A larger gain A for accuracy, shifts the bode diagram upwards and makes stability issue even more critical An evident advantage: a) The regulated output is the supply of the load

• circuit. A bigger capacitor is synergic in providing

both a clean reference and a more stable loop

Dominant pole at the output

Gain freq A

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Dominant pole at the output

2nd pole effects mitigation: a) Use a buffer to decouple stage A high impedance and parasitic Cp at Pout gate. The shift of the associated pole at higher frequency is paid with the introduction of an additional pole b) Add zeroes close to LDO GBW and quite before the high order poles

Vref R2 R1 Buff Pout Cp Cload A RC Cz ESR

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Dominant pole at the output

Suppose A=50, R=200K, Cp=100pF Cload from 680nF to 2.2uF C=0.5pF gm_buff=1/1000 Gmout_max=0.1 p2= RC = 1.6MHz p3= gm_buff/Cp =1.6MHz GBWmax= A*gmpout/Cload = 1.2MHz Feasibility achieved!

Vref R2 R1 Buff Pout Cp Cload Gm_in RC Cz ESR

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Dominant pole at Pout gate. It fits a Miller compensation approach for output pole splitting

• Immediate problems:

i) Bad HF PSRR: Pout acts like a Vin-referred diode in HF ii) too poor pole splitting: Cp attenuates the feedback across Pout and Cm to make pole split at gm_pout/[Cload *(1+Cp/Cm)]

LDO stability: is Miller compensation better?

Vref R2 R1 A Pout Cm Cp Cload

Example: assume 100uA min. load current, Cload=1uF and Cm=Cp=50pF Output pole splits at 160Hz, too low for a reasonable GBW achievement

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Am gain stage inserted to boost Gm_pout Total accuracy defined by the product A*Am. => Am value can be chosen independently from accuracy issues Pole splitting at OUT :

• Gm_pout boosted Am times.
• No attenuation from Cp:
• Excellent PSRR once Am virtual ground

tracks GND Am=30 splits output pole at 10 KHz. An input stage with 400nA tail current and Cm=60pF provides 45deg PM to ensure the feasibility of the approach

LDO stability: improved Miller compensation

Vref R2 R1 Am Pout Cm Cp Cload A

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LDO stability: improved Miller compensation

The pole splitting will be even more effective If Am is made greater WARNING: At HF, Cm acts like a short. The loop formed by Am, Pout and Cload is the same of the starting point one: still 2 low frequency poles fighting to be the dominant one. Bigger Am brings us back to the starting point!

Vref R2 R1 Am Pout Cm Cp Cload A Local HF loop

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a) choose a moderate value for Am, smaller than A in the dominant pole approach. This alleviates the stability requirements of the Miller local loop. b) Ensure the desired accuracy by means of the first stage gain A. Its DC value can be extremely high with no impact on stability. Only A stage input transconductance Gm should be small enough to guarantee loop stability with practical values of the compensating capacitor Cm.

Summarizing Miller

Vref R2 R1 Am Pout Cm Cp Cload A Local HF loop

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Noise concerns: Usually Gm of input stage is small and large noise is expected. Anyhow this holds only for the range below GBW which is in the order of few KHz. In this range usually flicker dominates the thermal contributes, hence small gm stage is not very detrimental. Wide band noise in Miller compensated LDO comes from the second stage which, being less critical in terms of stability and accuracy, may be optimized for this parameter

Summarizing Miller

Vref R2 R1 Am Pout Cm Cp Cload A Local HF loop

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LDO topologies – Miller vs. output dominant pole

General observation: forget 60deg phase margin. Not necessary indeed, this is not a signal amplifier and a ringing response is tolerated

Load dominant pole outperforms Miller thanks to:

1) no upper limit to load capacitor: cleaner regulated supply 2) lower power consumption (do not forget 100uA assumed in the Miller stage) 3) Smaller area (no compensating cap and less transistors) 4) simpler design (one loop only) 5) Faster startup: no slew rate limitation on an internal cap Miller outperforms the load dominant pole structure because of: 1) improved accuracy 2) Alleviated stability concerns 3) Improved HF noise performance

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Regardless the followed approach, it is a matter to stabilize a loop which comprises an internal closed loop structure.

• In the output dominant pole approach a closed feedback buffer is located between

the error amplifier output and the power PMOS gate

• In the Miller compensation approach, we identify the group made by Am Pout and

Cm as a closed loop block cascaded to the error amplifier block

Design stability strategy:

Vref R2 R1 Am Pout Cm Cp Cload A Local HF loop OUT Vin

R2 Gm_in

Vref

R1

Dominant pole at the output Miller compensated loop

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How the response of the local loop affects the global one is not straightforward. the same issue can be found in several other design solutions: Ahuja’s compensation, Nested Miller amplifiers, DCDC current mode switching regulators

Design stability strategy:

+

• +A

C1 C2 Vref 2*I2 Rz Cc Cload Iload Vfdbk I1 I1 Mnc Mpls Qo Cbe Ils

Ahuja’s compensation Nested Miller: 2 loops

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Current mode DCDC converter :

an inner, local, closed loop (red curve) embedded into an external one (blue curve) It is good to say something about before saying thanks and goodbye

Inner loop External loop

Design stability strategy:

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Just for getting started…..

This picture proves that this is stuff for strong people Despite 87deg phase margin, the transient simulation shows that the system is unstable How can it be? Even if something strange can be noticed…...

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How a closed loop Bode diagram changes if moving towards instability

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How a closed loop Bode diagram changes if moving towards instability

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How a closed loop Bode diagram changes if moving towards instability

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How a closed loop Bode diagram changes if moving towards instability

Up to this point we have always considered a positive phase margin: moving towards instability: Module diagram tends to peaking at GBW Phase diagram tends to provide sharper transitions In the next slides the waveform will consider increasingly negative phase margin: the loop becomes more and more unstable

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How a closed loop Bode diagram changes if moving towards instability

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How a closed loop Bode diagram changes if moving towards instability

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How a closed loop Bode diagram changes if moving towards instability

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Closed loop response

When the loop becomes unstable, the phase jump is upwards instead of being downwards This is due to the presence of positive real part complex conjugate poles it is well-known that right half plane poles mean instability If the loop gets more and more unstable, both module and phase profiles get smoother. The largest module peaking and the sharpest phase jump are corresponding to a 0° phase margin condition

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Stepping back: comments on the

• riginal Bode diagram
• Upwards phase jump:

UNSTABLE

• smooth profile in both

phase and module: => deep instability

• At very high frequency module roll off is huge (around 80dB/dec) to show much

more poles than zeroes. How could it be that phase displacement from DC is so small (few degrees) unless poles have positive real part?

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Closed loop response

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The local closed loop is here considered cascaded to a LF dominant pole. We have noticed that the associated pole is at its own GBW. Design targets global GBW lower than local loop GBW to achieve around 45deg PM In the resulting Bode diagrams, we remark: 1) a less stable local loop (red curve) improves the global loop phase margin: this is because the phase shift of the local loop tends to concentrate in a narrower range, causing a smaller phase shift at lower frequency 2) This is a trade-off with the increased module peaking, which is detrimental for the

• verall loop gain margin performance

poorly stable local loop peak at local loop GBW module phase fairly stable local loop

Better phase response if local loop is poorly damped abrupt phase shift at local loop GBW

0dB

Closed loop response inside global loop

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Local loop stability can be achieved by reducing its gm (i.e. less current) => the resulting global loop Bode diagram is stable, HF roll-off and phase shift values are now compatible, phase margin is safe enough (45°)……. Only crosscheck with transient before closing the lesson

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Closed loop response

Space left for transient simulation crosscheck

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Local loop stability can be achieved by reducing its gm (i.e. less current) OOOOPS! WHY transient still shows instability?????? CONFIDENTIAL Well, we have tried our worst to trigger this problem, which is somewhat rare. But it might happen…...Let us see why

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Closed loop response

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Local feedback impact on total stability

Slew rate limitation: A slew rate limitation causes a delay in the loop that is not evidenced in the AC analyses. Also a transient under moderate load variations does not evidence it. if a slew rate limitation occurs, it is often referred to the compensating capacitor. As this makes slower the slowest node on a loop, we may even say that this makes the loop more stable. But this also tells us, corroborated by simulation, that if a local loop has slew rate limitations, the global loop has an internal non dominant pole that it is slower than AC simulation foresees. Hence, in our case: High-order pole time constant τ is altered into an higher equivalent one, as if the pole shifts to lower

• frequency. Not taken into account in AC simulation.
• Always simulate large (0 to Imax) and fast (few ns) load current transient variations to

verify design robustness. Do not limit investigation to AC analyses 80

time

t t_eq

V

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Target: Operational amplifier with pull-up capability (load resistor to GND) A common source PMOS transistor ensures large source current Problem: Miller compensation brings Vdd noise at the output. Is it possible an architectural change to Improve PSRR at minimum cost?

Design example:

Vdd

A

Mout

Vout

Cc Cp Ib Vin RL CL

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Ahuja’s compensation: the AC feedback current from the output is injected into a cascode Mnc instead of reaching directly the gate of the output transistor.

• PSRR is determined by the source of the cascode: Choose gate bias to track GND
• stronger pole splitting (Cc/Cp as transfer function from output to dominant pole instead
• f Cc/(Cp+Cc))

Design example

Vin 2*I2 Cc Vfdbk I1 I1 Mnc Mpls Mpout Ils Cp

Vout

Ib RL CL

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The first attempt for the new approach is promising but gain margin is a bit too poor…

• nly 3dB

Design example

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The most obvious approach is to increase the compensating cap as a result, gain decreases and phase “looks” better accordingly to the expectation of an inexperienced eye

Design example

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Indeed large compensating cap Cc in Ahuja’s has a twofold effect

• Lower global GBW
• Increases gain of the local loop up to instability!

If unaware of the right half plane issue, both trivial expectation and numbers from AC analyses (GM and PM) seem to confirm that larger Cc values move in the desired direction. Hence one would insist on this way until the final bad surprise of a transient crosscheck….

Design example

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• It might be confusing: for instance if a correct,

but insufficient, modification brings from the blue to the purple phase waveform, the sharper profile makes think of an even more unstable condition and suggests the opposed strategy of modification!

Design example

• What to do?

A) Try to change something and hope that everything would be fine?

• It is unpractical: if not fully understood the AC vs. transient discrepancy, the solution would be

safe only if all the corners are simulated in transient, being AC unreliable. B) Abandon the Ajuha’s approach and accept poorer but stable Miller performance?

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C) Use a class A approach with NMOS pull-down for Miller optimal PSRR, accepting much more current consumption? D) Is there time to think about the Ahuja’s apparent contradiction and solve it? This would be great as it is sufficient to increase Cp to keep Cc/Cp constant. This prevents local loop instability when decreasing global loop GBW via larger Cc values

Design example

A

Mout

Vout

Cc Ib > Iload_max Vin RL CL Vin

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This simple, very low cost modification, ensures a big PSRR achievement vs. the starting point solution.

Design example