Layout Decomposition for Quadruple Patterning Lithography and Beyond
Bei Yu, David Z. Pan
Department of Electrical & Computer Engineering University of Texas at Austin, TX USA
06/03/2014
Supported by IBM scholarship, NSF, NSFC, SRC
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Layout Decomposition for Quadruple Patterning Lithography and Beyond - - PowerPoint PPT Presentation
Layout Decomposition for Quadruple Patterning Lithography and Beyond Bei Yu , David Z. Pan Department of Electrical & Computer Engineering University of Texas at Austin, TX USA 06/03/2014 Supported by IBM scholarship, NSF, NSFC, SRC 1 /
Department of Electrical & Computer Engineering University of Texas at Austin, TX USA
Supported by IBM scholarship, NSF, NSFC, SRC
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◮ Natural extension of triple patterning lithography (TPL) ◮ But with one more mask
◮ Delay of EUVL ◮ CAD tools: need to be prepared ◮ Resolve native conflict from triple patterning mask 1 mask 2 mask 3 mask 4
(a) (b)
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◮ Input layout patterns ◮ Minimum coloring distance mins
b c d a e
Stitch Candidate
b c d a1 e1 b e2 a2 d c b c d a1 e1 b e2 a2 d c
◮ Decomposed layout ◮ Minimize the conflict number & the stitch number
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ILP Odd-Cycle Partition Matching
ILP Graph Method Heuristic SDP
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x z y
(0, 0, 1) (0, 2
√ 2 3 , − 1 3)
(
√ 6 3 , − √ 2 3 , − 1 3)
(−
√ 6 3 , − √ 2 3 , − 1 3)
◮ Four unit vectors ◮ same color:
◮ different color:
◮ Greedy Mapping v.s. Backtrack Mapping
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◮ Linear runtime complexity: resolved one by one ◮ But, Any coloring order results in Local Optimality ◮ Example: order a-b-c-d-e
b d c a e a c d e b
(a)
b d c a e a c d e b
(b)
b d c a e
Half Pitch
(c)
b d c a e a c d e b
(d)
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◮ Three orders would be processed simultaneously ◮ Best solution would be selected ◮ Still Linear runtime complexity
3Round-Coloring
Degree-Coloring
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◮ Reduce the problem size ◮ Example:
component 2 component 1
a b c d e f (a)
component 2 component 1
a b c d e f
component 2 component 1
a b c d e f (b) (c)
rotated by 1
color 0 color 1 color 2 color 3
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C 3 , 5 4 C 5 , 3 1 5 C 6 , 2 8 8 C 7 , 5 5 2 S 1 , 4 8 8 S 3 8 , 4 1 7 S 3 5 , 9 3 2 S 3 8 , 5 8 4 S 1 5 , 8 5 Scaled Runtime
SDP+Backtrack SDP+Greedy Linear
20 40 60 80 100 C 4 3 2 C 4 9 9 C 8 8 C 1 , 3 5 5 C 1 , 9 8 C 2 , 6 7
◮ 500× cf. SDP+Backtrack ◮ 60× cf. SDP+Greedy
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S 3 5 , 9 3 2 S 3 8 , 5 8 4 S 1 5 , 8 5 Conflict #
SDP+Backtrack SDP+Greedy Linear
1 10 100 1,000 C 4 3 2 C 4 9 9 C 8 8 C 1 , 3 5 5 C 1 , 9 8 C 2 , 6 7 C 3 , 5 4 C 5 , 3 1 5 C 6 , 2 8 8 C 7 , 5 5 2 S 1 , 4 8 8 S 3 8 , 4 1 7
◮ Similar conflict # cf. SDP+Backtrack ◮ 67% Conflict # reduction cf. SDP+Greedy
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◮ Semidefinite programming (SDP) ◮ Linear color assignment ◮ GH-Tree based graph division
Circuit SDP+Backtrack SDP+Greedy Linear cn# st# CPU(s) cn# st# CPU(s) cn# st# CPU(s) C6288 19 2 2.4 19 2 0.49 19 5 0.005 C7552 1 1 0.3 1 1 0.05 1 4 0.001 S38417 4 1.45 4 0.21 4 0.001 S35932 5 20 8.11 5 20 0.62 5 25 0.009 S38584 3 4 1.66 7 3 0.3 3 6 0.008 S15850 6 5 2.7 7 5 0.4 5 15 0.007 avg. 5.7 6.0 2.77 6.5 5.83 0.35 5.5 9.8 0.005 ratio 1.0 1.0 1.0 1.15 0.97 0.12 0.97 1.64 0.002 ◮ Linear color assignment: best conflict #, 500× speed-up
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ILP Odd-Cycle Partition Matching
ILP Graph Method Heuristic SDP Linear 3-Cut Removal Graph Method SDP
◮ First attempt for Quadrule Patterning and Beyond ◮ Generic & Robust to General Patterning ◮ Facilitaing the advancement of Multiple Patterning
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