triple patterning lithography tpl layout decomposition
play

Triple Patterning Lithography (TPL) Layout Decomposition using - PowerPoint PPT Presentation

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting Bei Yu , Jhih-Rong Gao, and David Z. Pan Dept. of Electrical & Computer Engineering University of Texas at Austin Supported in part by NSF, SRC, Oracle, and NSFC


  1. Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting Bei Yu , Jhih-Rong Gao, and David Z. Pan Dept. of Electrical & Computer Engineering University of Texas at Austin Supported in part by NSF, SRC, Oracle, and NSFC

  2. Triple Patterning Lithography (TPL) t LELE-LE: Extend from LELE type double patterning t Main challenge: layout decomposition t Native conflicts Target/ Final 1st Mask a b 2nd Mask c d 3rd Mask 2

  3. TPL with End-Cutting (LELE-EC) t New TPL manufacturing process [Lin, ISPD’12] t LELE + end cutting (trim mask) Target/ Final 1st Mask 2nd Mask Trim Mask 3

  4. Why LELE-EC ? t Remove 4-clique native conflict in LELE-LE › Common even in regular layout a b c d t Square-shaped Line-ends [Y. Bordovsky, SPIE’05] [B. Lin, ISPD’12] 4

  5. LELE-EC: no free lunch t New design constraints: › Min distance among end-cuts Stitch Solution to simultaneously assign colors and assign end-cuts 5

  6. Previous Works t LELE-LE layout decomposition › Mathematical programming [ Cork, SPIE’08; Yu, ICCAD’11 ] › Heuristic methods [ Ghaida, SPIE’12; Fang, DAC’12 ] › Polynomial time checking [ Tian, ICCAD’12/SPIE’13 ] t LELE-LE aware routing [ Ma, DAC’12; Lin, ICCAD’12 ] t First study for LELE-EC type triple patterning › Can borrow previous idea ? 6

  7. Layout Decomposition Flow Layout End-cut Candidate Generation Decomposition Rules Layout Graph and End-cut Graph Simplification Decomposition on Graph ILP Formulation Output Masks 7

  8. End-cut Candidate Generation t Edge-edge (a) (b) (c) (d) t Corner-corner (a) (b) (c) (d) 8

  9. Layout Decomposition Flow Layout End-cut Candidate Generation Decomposition Rules Layout Graph and End-cut Graph Simplification Decomposition on Graph ILP Formulation Output Masks 9

  10. Layout Graph t Layout topologies è graph model t Layout graph: feature info and end-cut candidate info 1 2 1 2 3 4 3 4 5 6 5 6 7 7 1 2 1- 1 2 2 1-3 1-4 2-4 3 4 3 4 3-4 Conflict edge that can be 3-5 4-6 5 6 removed by end-cut 5 6 5-6 6-7 7 5-7 7 10

  11. End-cut graph t Some end-cuts are conflict, while some can be merged t New graph to store the end-cut relationships › conflict edge (solid): two candidates are conflict › merge edge (dash): two candidates can be merged 1- 1 2 2 1-3 1-4 2-4 3 4 3-4 ec 14 and ec 46 have conflict 1-4 1-2 3-5 4-6 5 6 5-6 1-3 6-7 3-4 2-4 5-7 7 1 2 3-5 4-6 5-6 ec 35 and ec 46 can be 3 4 merged into one endcut 6-7 5-7 Conflict edge that can be removed by end-cut 5 6 7 11

  12. Layout Decomposition Flow Layout End-cut Candidate Generation Decomposition Rules Layout Graph and End-cut Graph Simplification Decomposition on Graph ILP Formulation Output Masks 12

  13. ILP Formulation t CE: edge set of layout graph t EE: conflict-edge set of end-cut graph Exception: x 1 =x 2 , since ec 13 =ec 23 =1, ec 12 can be 0 1 1 1 1-3 3 1-2 3 2 2 2 2-3 13

  14. ILP Formulation (cont.) Non-linear 1 1 1 1-3 3 1-2 3 2 2 2 2-3 14

  15. ILP Formulation (cont.) t Consider stitch insertion t SE: set of stitch edge candidates Other constraints in previous ILP 15

  16. Layout Decomposition Flow Layout End-cut Candidate Generation Decomposition Rules Layout Graph and End-cut Graph Simplification Decomposition on Graph ILP Formulation Output Masks t Independent Component Computation t Bridge Computation t End-Cut Pre-Selection 16

  17. Experimental Results t Implement in C++ t 3.0GHz Linux machine with 32G RAM t ISCAS 85&89 benchmarks from [Yu, ICCAD’11] t Scaled to 14nm nodes t ILP solver: GUROBI 17

  18. Without or With stitch? t Cost comparison (cost = conflict# + 0.1 * stitch#) t Runtime comparison 600 50 45 ILP w/o. stitch 500 ILP w. stitch 40 Cost = Conflict + 0.1 * Stitch 35 400 ILP w/o. stitch 30 Runtime (s) ILP w. stitch 25 300 20 200 15 10 100 5 0 0 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 cost runtime 18

  19. Conflict Example t Irregular via array is dangerous 19

  20. Conflict Num 10 15 20 25 30 35 40 45 50 0 5 LELE-LE v.s. LELE-EC t LELE-LE decomposer from [Fang, DAC’12] C432 C499 C880 C1,355 C1,908 C2,670 conflict C3,540 LELEEC LELELE C5,315 C6,288 C7,552 S1,488 S38,417 S35,932 S38,584 S15,850 20 Stitch Num 100 150 200 250 300 350 50 0 C432 C499 C880 C1,355 C1,908 C2,670 C3,540 stitch C5,315 C6,288 C7,552 S1,488 LELEEC LELELE S38,417 S35,932 S38,584 S15,850

  21. Conclusion and Future Works t First LELE-EC layout decomposition problem t ILP formulation and speedup techniques t Less conflict & stitch compared with LELE-LE TPL is candidate for 14nm node. t More research on TPL(LELEEC)-aware design 21

  22. Thank You 22

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend


More recommend