Lab 5 preview Hung-Wei Tseng Announcement Lab 4 due Thursday - PowerPoint PPT Presentation

Lab 5 preview Hung-Wei Tseng

Announcement • Lab 4 due Thursday before 5:30pm! • Interview with any of us • Lab 5 & 6 due next Thursday • No extension • Come and have some pizza together next Friday @ 6p! � 2

In Lab 5... • Pipeline your processor • Teach it “walk”, and teach it “fly” • A working pipeline processor is better than a crappy 5-stage • Your processor does not have to be 5-stage • Please complete the lab as soon as possible � 3


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 In lab4, you already have... RegDst size_in Jump re_in MemToReg control 
 Func_in inst[31:26], inst[5:0] unit we_in 1 
 ALUSrc m 
 u 
 RegWrite x inst[25:0] Shi> 0 1 le> 2 26 28 m 
 PC+4[31:28] u 
 x Add Add Shi> 0 4 le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register Memory Memory inst[20:16] Data 1 Read Reg 2 Read inst[31:0] Read File 0 
 m 
 PC Address u 
 Address ALU Write Reg Read 1 
 x Data 1 inst[15:11] 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 BranchOut x JumpOut 0 sign- 
 1 16 32 extend � 4


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 In lab5, we are going to pipeline it! RegDst size_in Jump re_in MemToReg control 
 Func_in inst[31:26], inst[5:0] unit we_in 1 
 ALUSrc m 
 u 
 RegWrite x inst[25:0] Shi> 0 1 le> 2 26 28 m 
 PC+4[31:28] u 
 x Add Add Shi> 0 4 le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register Memory Memory inst[20:16] Data 1 Read Reg 2 Read inst[31:0] Read File 0 
 m 
 PC Address u 
 Address ALU Write Reg Read 1 
 x Data 1 inst[15:11] 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 BranchOut x JumpOut 0 sign- 
 1 16 32 extend � 5


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 It’s not just adding pipeline registers! RegDst size_in Jump re_in MemToReg control 
 Func_in inst[31:26], inst[5:0] unit we_in 1 
 ALUSrc m 
 u 
 RegWrite x inst[25:0] Shi> 0 1 le> 2 26 28 m 
 PC+4[31:28] u 
 x Add Add Shi> 0 4 le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register Memory Memory inst[20:16] Data 1 Read Reg 2 Read inst[31:0] Read File PC Address Address ALU Write Reg Read 1 
 Data 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 BranchOut x JumpOut 0 sign- 
 1 16 32 extend m 
 0 
 u 
 x 1 inst[15:11] � 6

Sol. of data hazard II: Forwarding • The result is available after EXE and MEM stage, but publicized in WB! • The data is already there, we should use it right away! • Also called bypassing add $1, $2, $3 
 IF ID EXE lw $4, 0($1) 
 IF ID sub $5, $2, $4 
 IF sub $1, $3, $1 
 We can obtain the result here! sw $1, 0($5) � 7

Sol. of data hazard II: Forwarding • Take the values, where ever they are! IF ID EXE MEM WB add $1, $2, $3 
 lw $4, 0($1) 
 IF ID EXE MEM WB sub $5, $2, $4 
 IF ID ID EXE MEM WB sub $1, $3, $1 
 IF IF ID EXE MEM WB sw $1, 0($5) IF ID EXE MEM WB 10 cycles! CPI == 2 (Not optimal, but much better!) � 8

Design a forwarding unit • How many of the following inputs are required for forwarding the result from the previous instruction (Ins#1) to the EXE stage of the current instruction (Ins#2)? • • Rd of Ins#2 Rs of Ins#1 • • Rs of Ins#2 Rt of Ins#1 • • Rt of Ins#2 ReadData 2 of Ins #1 • • ReadData 2 of Ins #2 Control signals of Ins #1 • Rd of Ins#1 opcode rs rt rd shift amount funct A. 5 opcode rs rt immediate / offset B. 6 We need to know the following: C. 7 1. If the ins#1 update a register (RegWrite) D. 8 2. If the destination register of ins #1 (rt, td) is a source of ins #2 
 If ins #1 is R-type: rs, rt of ins #2 == rd of ins #1 
 E. 9 � 9 If ins #1 is I-type: rs, rt of ins #2 == rt of ins #1

When can/should we forward data? • If the instruction entering the EXE stage consumes a result from a previous instruction that is entering MEM stage or WB stage • A source of the instruction entering EXE stage is the destination of an instruction entering MEM/WB stage • The previous instruction must be an instruction that updates register file � 10


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Forwarding in hardware PCSrc Control of Ins#1 Control of Ins#2 RegWrite 1 
 MEM/WB IF/ID ID/EX EX/MEM m 
 u 
 x W W W 0 Contr M M ol E inst[31:25],inst[5:0] Add Add Shi> 4 RegWrite MemWrite le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register m 
 Memory u 
 Memory x inst[20:16] Data 1 MemtoReg Read Reg 2 Zero Read Read ForwardA File PC Address Address ALU inst[31:0] Write Reg Read 1 
 Data 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 x ALUop 0 sign- 
 1 inst[15:11] MemRead 16 32 RegDst extend ForwardB 0 
 m 
 u 
 x 1 ALU result of previous instruction (Ins#1) Ins#1 ForwardA forwardin curernt instruction (Ins#2) g 
 destination of Ins#1 ForwardB Rs of Ins#2 How about load? ALUSrc � 11 Rt of Ins#2


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ALU/MEM Forwarding in hardware result of Ins#1 PCSrc Control of Ins#1 RegWrite 1 
 MEM/WB IF/ID ID/EX EX/MEM m 
 u 
 x W W W 0 Contr M M ol E inst[31:25],inst[5:0] Add Add Shi> 4 RegWrite MemWrite le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register m 
 Memory u 
 Memory x inst[20:16] Data 1 MemtoReg Read Reg 2 Zero Read Read ForwardA File PC Address Address ALU inst[31:0] Write Reg Read 1 
 Data 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 x ALUop 0 sign- 
 1 inst[15:11] MemRead 16 32 RegDst extend ForwardB 0 
 m 
 u 
 x 1 ForwardA forwardin g 
 ForwardB Rd of Ins#1 ALUSrc � 12

There is still a case that we have to stall... lw generates result at • Revisit the following code: MEM stage, we have IF ID EXE MEM WB add $1, $2, $3 
 to stall lw $4, 0($1) 
 IF ID EXE MEM WB sub $5, $2, $4 
 IF ID ID EXE MEM WB sub $1, $3, $1 
 IF IF ID EXE MEM WB sw $1, 0($5) IF ID EXE MEM WB • If the instruction entering EXE stage depends on a load instruction that does not finish its MEM stage yet, we have to stall! • We call this hazard detection We need to know the following: 1. If an instruction in EX/MEM updates a register (RegWrite) 2. If an instruction in EX/MEM reads memory (MemRead) 3. If the destination register of EX/MEM is a source of ID/EX � 13 (rs, rt of ID/EX == rt of EX/MEM #1)


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Hazard detection with forwarding PCWrite hazard ID/EX.MemRead PCSrc detection 
 IF/IDWrite unit RegWrite 1 
 MEM/WB IF/ID ID/EX EX/MEM m 
 u 
 x W W W 0 m 
 Contr u 
 x M M 0 ol E inst[31:25],inst[5:0] Add Add Shi> 4 RegWrite MemWrite le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register m 
 Memory u 
 Memory x inst[20:16] Data 1 MemtoReg Read Reg 2 Zero Read Read ForwardA File PC Address Address ALU inst[31:0] Write Reg Read 1 
 Data 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 x ALUop 0 sign- 
 1 inst[15:11] MemRead 16 32 RegDst extend ForwardB 0 
 m 
 u 
 x 1 ForwardA forwardin g 
 ForwardB ALUSrc � 14


 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Hazard detection & stall PCWrite hazard ID/EX.MemRead PCSrc detection 
 IF/IDWrite unit Insert a “noop” if we need to stall RegWrite 1 
 MEM/WB IF/ID ID/EX EX/MEM m 
 u 
 x W W W 0 m 
 Contr u 
 x M M 0 ol E inst[31:25],inst[5:0] Add Add Shi> 4 RegWrite MemWrite le> 2 inst[25:21] Data Instruc(on Read Reg 1 Read Register Memory Memory inst[20:16] Data 1 MemtoReg Read Reg 2 Zero Read ALUSrc Read File PC Address Address ALU inst[31:0] Write Reg Read 1 
 Data 0 
 Data 2 m 
 Write Data u 
 m 
 Write Data x u 
 x ALUop 0 sign- 
 1 inst[15:11] MemRead 16 32 RegDst extend Check if the destination register of EX == source register of the 0 
 m 
 u 
 instruction in ID x 1 Check if the destination register of MEM == source register of the instruction in ID � 15

Dealing with hazards • In standard 5-stage MIPS pipeline, you will meet • Data hazard • Stall • Data forwarding (bonus) • Control hazard • Stall • You may move branch resolution to the ID stage • Branch prediction (bonus) � 16

Instead of 5-stage • 4-stage • For example, IF, ID, EX+MEM, WB • Fewer stall conditions • Longer cycle time • 3-stage • 2-stage • IF+ID, the rest • IF alone cannot be a pipeline stage � 17

Benchmarks • In this lab, we will use the following programs • No branch hello world • Hello world with branch • Fibonacci number • Start with PC 0x400000 • A set of testing scripts � 18

Interview questions • Show the schematics • Show the waveforms of three benchmarks until the end • Measure the IC, total cycles,CPI • Report the Fmax • We can calculate the performance of your processor! � 19