Lab 5 preview Hung-Wei Tseng Announcement Lab 4 due Thursday - - PowerPoint PPT Presentation

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Lab 5 preview Hung-Wei Tseng Announcement Lab 4 due Thursday - - PowerPoint PPT Presentation

Mar 11, 2024 114 likes •339 views

Lab 5 preview Hung-Wei Tseng Announcement Lab 4 due Thursday before 5:30pm! Interview with any of us Lab 5 & 6 due next Thursday No extension Come and have some pizza together next Friday @ 6p! 2 In Lab 5...

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SLIDE 1

Lab 5 preview

Hung-Wei Tseng

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SLIDE 2

Announcement

  • Lab 4 due Thursday before 5:30pm!
  • Interview with any of us
  • Lab 5 & 6 due next Thursday
  • No extension
  • Come and have some pizza together next Friday @

6p!

2

slide-3
SLIDE 3

In Lab 5...

  • Pipeline your processor
  • Teach it “walk”, and teach it “fly”
  • A working pipeline processor is better than a crappy 5-stage
  • Your processor does not have to be 5-stage
  • Please complete the lab as soon as possible

3

slide-4
SLIDE 4

In lab4, you already have...

4

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

JumpOut BranchOut Func_in RegDst Jump re_in MemToReg we_in ALUSrc RegWrite

Add Shi> le> 2

m
 u
 x

1 
 
 
 
 


inst[25:0] Shi> le> 2 26 28

PC+4[31:28] size_in

control
 unit

inst[31:26], inst[5:0]

m
 u
 x

1
 
 
 
 


slide-5
SLIDE 5

In lab5, we are going to pipeline it!

5

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[15:11] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

JumpOut BranchOut Func_in RegDst Jump re_in MemToReg we_in ALUSrc RegWrite

Add Shi> le> 2

m
 u
 x

1 
 
 
 
 


inst[25:0] Shi> le> 2 26 28

PC+4[31:28] size_in

control
 unit

inst[31:26], inst[5:0]

m
 u
 x

1
 
 
 
 


slide-6
SLIDE 6

It’s not just adding pipeline registers!

6

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16]

inst[15:11]

inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

JumpOut BranchOut Func_in RegDst Jump re_in MemToReg we_in ALUSrc RegWrite

Add Shi> le> 2

m
 u
 x

1 
 
 
 
 


inst[25:0] Shi> le> 2 26 28

PC+4[31:28] size_in

control
 unit

inst[31:26], inst[5:0]

m
 u
 x

1
 
 
 
 


slide-7
SLIDE 7
  • Sol. of data hazard II: Forwarding
  • The result is available after EXE and MEM stage,

but publicized in WB!

  • The data is already there, we should use it right

away!

  • Also called bypassing

7

add $1, $2, $3
 lw $4, 0($1)
 sub $5, $2, $4
 sub $1, $3, $1
 sw $1, 0($5)

IF EXE ID IF ID IF

We can obtain the result here!

slide-8
SLIDE 8
  • Sol. of data hazard II: Forwarding
  • Take the values, where ever they are!

8

add $1, $2, $3
 lw $4, 0($1)
 sub $5, $2, $4
 sub $1, $3, $1
 sw $1, 0($5)

IF EXE ID IF ID IF WB MEM EXE ID IF MEM WB ID MEM EXE WB IF ID MEM EXE WB IF ID MEM EXE WB

10 cycles! CPI == 2 (Not optimal, but much better!)

slide-9
SLIDE 9

Design a forwarding unit

  • How many of the following inputs are required for

forwarding the result from the previous instruction (Ins#1) to the EXE stage of the current instruction (Ins#2)?

9

  • Rd of Ins#2
  • Rs of Ins#2
  • Rt of Ins#2
  • ReadData 2 of Ins #2
  • Rd of Ins#1
  • Rs of Ins#1
  • Rt of Ins#1
  • ReadData 2 of Ins #1
  • Control signals of Ins #1
  • A. 5
  • B. 6
  • C. 7
  • D. 8
  • E. 9

We need to know the following:

  • 1. If the ins#1 update a register (RegWrite)
  • 2. If the destination register of ins #1 (rt, td) is a source of ins #2


If ins #1 is R-type: rs, rt of ins #2 == rd of ins #1
 If ins #1 is I-type: rs, rt of ins #2 == rt of ins #1

  • pcode

rs rt rd shift amount funct

  • pcode

rs rt immediate / offset

slide-10
SLIDE 10

When can/should we forward data?

  • If the instruction entering the EXE stage consumes a

result from a previous instruction that is entering MEM stage or WB stage

  • A source of the instruction entering EXE stage is the destination
  • f an instruction entering MEM/WB stage
  • The previous instruction must be an instruction that updates

register file

10

slide-11
SLIDE 11

Forwarding in hardware

11

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

m
 u
 x

1
 
 
 
 


Add Shi> le> 2 ALUSrc

MemtoReg

MemRead

RegDst

RegWrite MemWrite PCSrc

Zero

IF/ID ID/EX EX/MEM MEM/WB

inst[15:11] ALUop

Contr

  • l

W M E W M W

RegWrite

forwardin g


m
 u
 x

ForwardA ForwardB ForwardA ForwardB

destination of Ins#1 Rs of Ins#2 Rt of Ins#2 ALU result of Ins#1 Control of Ins#1 Control of Ins#2

inst[31:25],inst[5:0]

previous instruction (Ins#1) curernt instruction (Ins#2)

How about load?

slide-12
SLIDE 12

Forwarding in hardware

12

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

m
 u
 x

1
 
 
 
 


Add Shi> le> 2 ALUSrc

MemtoReg

MemRead

RegDst

RegWrite MemWrite PCSrc

Zero

IF/ID ID/EX EX/MEM MEM/WB

inst[15:11] ALUop

Contr

  • l

W M E W M W

RegWrite

forwardin g


m
 u
 x

ForwardA ForwardB ForwardA ForwardB

Rd of Ins#1 ALU/MEM result of Ins#1 Control of Ins#1

inst[31:25],inst[5:0]

slide-13
SLIDE 13

There is still a case that we have to stall...

  • Revisit the following code:

13

add $1, $2, $3
 lw $4, 0($1)
 sub $5, $2, $4
 sub $1, $3, $1
 sw $1, 0($5)

IF EXE ID IF ID IF WB MEM EXE ID IF MEM WB ID MEM EXE WB IF ID MEM EXE WB IF ID MEM EXE WB

lw generates result at MEM stage, we have to stall

  • If the instruction entering EXE stage depends on a

load instruction that does not finish its MEM stage yet, we have to stall!

  • We call this hazard detection

We need to know the following:

  • 1. If an instruction in EX/MEM updates a register (RegWrite)
  • 2. If an instruction in EX/MEM reads memory (MemRead)
  • 3. If the destination register of EX/MEM is a source of ID/EX

(rs, rt of ID/EX == rt of EX/MEM #1)

slide-14
SLIDE 14

Hazard detection with forwarding

14

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

m
 u
 x

1
 
 
 
 


Add Shi> le> 2 ALUSrc

MemtoReg

MemRead

RegDst

RegWrite MemWrite PCSrc

Zero

IF/ID ID/EX EX/MEM MEM/WB

inst[15:11] ALUop

Contr

  • l

W M E W M W

RegWrite

forwardin g


m
 u
 x

ForwardA ForwardB ForwardA ForwardB

hazard detection
 unit

ID/EX.MemRead PCWrite IF/IDWrite

m
 u
 x

inst[31:25],inst[5:0]

slide-15
SLIDE 15

Hazard detection & stall

15

Read Address

Instruc(on Memory

PC ALU Write Data 4 Add Read Data 1 Read Data 2 Read Reg 1 Read Reg 2 Write Reg

Register File

inst[25:21] inst[20:16] inst[31:0]

m
 u
 x

0
 
 1

m
 u
 x

0
 
 
 
 
 
 1

sign-
 extend

32 16

Data Memory

Address Read Data

m
 u
 x

1
 
 
 
 
 
 
 


Write Data

m
 u
 x

1
 
 
 
 


Add Shi> le> 2

MemtoReg

MemRead

RegDst

RegWrite MemWrite PCSrc

Zero

IF/ID ID/EX EX/MEM MEM/WB

inst[15:11] ALUop

Contr

  • l

W M E W M W

RegWrite

ALUSrc hazard detection
 unit

ID/EX.MemRead PCWrite IF/IDWrite

m
 u
 x

Check if the destination register of EX == source register of the instruction in ID Check if the destination register of MEM == source register of the instruction in ID Insert a “noop” if we need to stall

inst[31:25],inst[5:0]

slide-16
SLIDE 16

Dealing with hazards

  • In standard 5-stage MIPS pipeline, you will meet
  • Data hazard
  • Stall
  • Data forwarding (bonus)
  • Control hazard
  • Stall
  • You may move branch resolution to the ID stage
  • Branch prediction (bonus)

16

slide-17
SLIDE 17

Instead of 5-stage

  • 4-stage
  • For example, IF, ID, EX+MEM, WB
  • Fewer stall conditions
  • Longer cycle time
  • 3-stage
  • 2-stage
  • IF+ID, the rest
  • IF alone cannot be a pipeline stage

17

slide-18
SLIDE 18

Benchmarks

  • In this lab, we will use the following programs
  • No branch hello world
  • Hello world with branch
  • Fibonacci number
  • Start with PC 0x400000
  • A set of testing scripts

18

slide-19
SLIDE 19

Interview questions

  • Show the schematics
  • Show the waveforms of three benchmarks until the end
  • Measure the IC, total cycles,CPI
  • Report the Fmax
  • We can calculate the performance of your processor!

19

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SLIDE 20

Lab 6: Optimization!

  • Data forwarding
  • Branch prediction
  • Cache
  • Superscalar
  • Special bonus for fastest processor

20

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SLIDE 21

Don’t forget to come by 8/2 6pm @ WLH 2111

21