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K Maps in higher dimensions, Elements of Sequential Circuits (Latches)

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

1

Review Some Definitions

• Complement: variable with a bar over it

A, B, C

• Literal: variable or its complement

A, A, B, B, C, C

• Implicant: product of literals

ABC, AC, BC

• Implicate: sum of literals

(A+B+C), (A+C), (B+C)

• Minterm: product that includes all input variables

ABC, ABC, ABC

• Maxterm: sum that includes all input variables

(A+B+C), (A+B+C), (A+B+C)

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Minimum Product of Sum

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Given f (a,b,c) = Σm (3, 5) + Σd (0, 4)

0 2 6 4 1 3 7 5

X 0 0 X 0 1 0 1

ab c 00 01 11 10 1 Prime Implicates: Essential Primes Implicates: Min exp: f(a,b,c) =

Minimum Product of Sum

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Given f (a,b,c) = Σm (3, 5) + Σd(0, 4)

0 2 6 4 1 3 7 5

X 0 0 X 0 1 0 1

ab c 00 01 11 10 1 Prime Implicates: ΠM (0, 1), ΠM (0, 2, 4, 6), ΠM (6, 7) Essential Primes Implicates: ΠM (0, 1), ΠM (0, 2, 4, 6), ΠM(6, 7) Min exp: f(a,b,c) = (a+b)(c )(a’+b’)

Corresponding Circuit

a b a’ b’ c f(a,b,c,d)

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Min exp: f(a,b,c) = (a+b)(c )(a’+b’)

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

1 0 0 1 1 0 0 X 0 0 0 0 1 0 1 X

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ab cd 00 01 00 01 11 10 11 10

• Reduce the following to a POS form
• First find the essential prime implicates

Minimum product of sum: Ex 2

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

1 0 0 1 1 0 0 X 0 0 0 0 1 0 1 X

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ab cd 00 01 00 01 11 10 11 10

• Reduce the following to a POS form
• First find the essential prime implicates

Minimum product of sum: Ex2

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

1 0 0 1 1 0 0 X 0 0 0 0 1 0 1 X

8

ab cd 00 01 00 01 11 10 11 10

• Reduce the following to a POS form
• First find the essential prime implicates

Minimum product of sum: Ex 2

Min product of sums: Ex3

Given f(a,b,c,d) = ΠM(3, 11, 12, 13, 14). ΠD(4, 8, 10)

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 9

ab cd 00 01 11 10 00 01 11 10

K-map

Min product of sums: Ex3

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a d

1 X 0 X 1 1 0 1 0 1 1 0 1 1 0 X

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

ab 00 01 11 10 cd 00 01 11 10 Given f(a,b,c,d) = ΠM(3, 11, 12, 13, 14). ΠD(4, 8, 10)

Prime Implicates: ΠM (3,11), ΠM (12,13), ΠM(10,11), ΠM (4,12), ΠM (8,10,12,14) PI Q: Which of the following is a non-essential prime implicate?

• A. ΠM(3,11)
• B. ΠM(12,13)
• C. ΠM(10,11)
• D. ΠM(8,10,12,14)

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a d

1 X 0 X 1 1 0 1 0 1 1 0 1 1 0 X

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10

ab 00 01 11 10 cd 00 01 11 10

12 0 2 6 4 1 3 7 5

X 0 1 0 1 0 0 X

ab c 00 01 11 10 1

(V) (25pts) (Karnaugh Map) Use Karnaugh map to simplify function f (a, b, c) = Σ m(1, 6) +Σ d(0, 5). List all possible minimal product of sums expres-

• sions. Show the Boolean expressions. No need for the logic diagram.

13 0 2 6 4 1 3 7 5

X 0 1 0 1 0 0 X

ab c 00 01 11 10 1

Five variable K-map

0 4 12 8

c d b e

1 5 13 9 3 7 15 11 2 6 14 10 16 20 28 24

c d b e a

17 21 29 25 19 23 31 27 18 22 30 26

Neighbors of m5 are: minterms 1, 4, 7, 13, and 21 Neighbors of m10 are: minterms 2, 8, 11, 14, and 26

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a=0 a=1 bc de 00 01 11 10 00 01 11 10 00 01 11 10

Reading a Five variable K-map

0 4 12 8

c d b e

1 5 13 9 3 7 15 11 2 6 14 10 16 20 28 24

c d b e a

17 21 29 25 19 23 31 27 18 22 30 26 15

a=0 a=1 bc de 00 01 11 10 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Six variable K-map

d e c f d e c d e c f

48 52 60 56

d e c b

49 53 61 57 51 55 63 59 50 54 62 58

a

32 36 44 40 33 37 45 41 35 39 47 43 34 38 46 42

f f

0 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 16 20 28 24 17 21 29 25 19 23 31 27 18 22 30 26 16

bc de ab=(0,0) ab=(0,1) ab=(1,0) ab=(1,1)

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we'll need a 4-variable Karnaugh map for each of the 3 output functions

Design example: two-bit comparator

block diagram LT EQ GT A B < C D A B = C D A B > C D A B C D N1 N2 A B C D LT EQ GT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 and truth table

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A' B' D + A' C + B' C D B C' D' + A C' + A B D' LT = EQ = GT = K-map for EQ K-map for LT K-map for GT

Design example: two-bit comparator (cont’d)

1

D A

1 1 1 1 1

B C

1 1

D A

1 1

B C

1 1 1 1 1

D A

1

B C

= (A xnor C) • (B xnor D) LT and GT are similar (flip A/C and B/D) A' B' C' D' + A' B C' D + A B C D + A B' C D’ Source: Rosing

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block diagram and truth table 4-variable K-map for each of the 4

• utput functions

A2 A1 B2 B1 P8 P4 P2 P1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Design example: 2x2-bit multiplier

P1 P2 P4 P8 A1 A2 B1 B2

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K-map for P8 K-map for P4 K-map for P2 K-map for P1

Design example: 2x2-bit multiplier (cont’d)

B1 A2

1 1 1

A1 B2

1 1

B1 A2

1 1

A1 B2

1 1

B1 A2

1 1 1 1

A1 B2 B1 A2

1

A1 B2

What is a sequential circuit?

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“A circuit whose output depends on current inputs and past outputs” “A circuit with memory”

Memory / Time steps Clock

xi yi si yi=fi(St,X) si

t+1=gi(St,X)

Why do we need circuits with ‘memory’?

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• Circuits with memory can be used to store data
• Complex systems often consist of circuits that

perform a sequence of tasks

Memory Hierarchy

23

Hard disk Main Memory Cache Registers

• What are registers made of?

To the flip-flop!

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• The most basic memory element:

The capacitive load

Q Q Q Q I1 I2 I2 I1

Fundamental Memory Mechanism

Q Q Q Q I1 I2 I2 I1

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How is this circuit different from a combinational circuit?

• A. Two outputs: Q, Q’
• B. Feedback loop
• C. No external inputs
• D. Both B and C
• E. None of the above

Does this circuit really remember?

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Q Q I1 I2 1 1

– Q = 0: then Q’ = 1 and Q = 0

Q Q I1 I2 1 1

– Q = 1: then

Bi-stable circuit

Q Q I1 I2 1 1

• Bistable circuit stores 1 bit of

state in the state variable, Q (or Q’ )

• But there are no inputs to

control the state

Q Q I1 I2 1 1

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SR (Set/Reset) Latch

R S Q Q N1 N2

• SR Latch
• Consider the four possible cases:

§ S = 1, R = 0: set output to ‘1’ § S = 0, R = 1: (reset) output to ‘0’ § S = 0, R = 0: store – output should be unchanged § S = 1, R = 1: Trouble!

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(S+Q)’

SR Latch Analysis

§ S = 1, R = 0: § S = 0, R = 1:

R S Q Q N1 N2 1

R S Q Q N1 N2 1

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SR Latch Analysis

§ S = 0, R = 0:

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R S Q Q N1 N2

SR Latch Analysis

§ S = 0, R = 0:

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R S Q Q N1 N2

What happens if Qprev=0 and Q’prev=0? A. The output Q toggles B. The output Q remains 0 and Q’ changes to 1 C. The output Q becomes 1 and Q’ remains 0

SR Latch Analysis

– S = 1, R = 1:

R S Q Q N1 N2 1 1

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