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Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE W4840 Spring 2011 Final Project
Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE - - PowerPoint PPT Presentation
Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE - - PowerPoint PPT Presentation
Jaiseung Bang, Vincent Liao, Arunagiri Venkatesan, David Yang CSEE W4840 Spring 2011 Final Project The Idea Downscaling Silhouette Generation - = Downscaling High Level Overview Camera VGA Monitor Altera DE2 Board 640x480
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Downscaling
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Silhouette Generation
- ‑ ¡
= ¡
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Downscaling
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High Level Overview
Camera
Background Capture Button Mode Buttons 7 Segment Displays
VGA Monitor
Altera Cyclone II FPGA
ADV7181
640x480 NTSC Video via Composite YCbCr VGA signals I2C
Altera DE2 Board
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Architecture
NIOS CPU
VGA Controller Silhouette Generator Downscaler Video Decoder
YCbCr video from ADV7181 YCbCr data and X/Y coordinates
Foreground RAM Background RAM I2C Config
downscaled data and X/Y coordinates coordinates
- f detected
silhouette ball data
SRAM
downscaled data and X/Y coordinates to VGA display to 7 seg displays from mode buttons from background capture button I2C to ADV7181
Data Transfer
Avalon Bus
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Design Decisions
- Block RAM
- 27MHz Clock
- Game Change
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Issues
- RAM Issue
- Clock Issue
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Goalie Mode
block green balls
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Dodge Mode
avoid red balls
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Ninja Mode
block green balls
avoid red balls
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Lessons Learned
- TD_Reset
- 1 Dimensional Arrays
- 27Mhz VGA Clock
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