Zellescher Weg 12 Trefftz-Bau/HRSK 151 Phone +49 351 - 463 - 39871 Guido Juckeland (guido.juckeland@tu-dresden.de)
Center for Information Services and High Performance Computing (ZIH)
Introduction to High Performance Computing at ZIH Architecture of - - PowerPoint PPT Presentation
Center for Information Services and High Performance Computing (ZIH) Introduction to High Performance Computing at ZIH Architecture of the PC Farm (Deimos) Zellescher Weg 12 Trefftz-Bau/HRSK 151 Phone +49 351 - 463 - 39871 Guido Juckeland
Zellescher Weg 12 Trefftz-Bau/HRSK 151 Phone +49 351 - 463 - 39871 Guido Juckeland (guido.juckeland@tu-dresden.de)
Center for Information Services and High Performance Computing (ZIH)
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1292 AMD Opteron x85 Dual-Core CPUs (2,6 GHz) 726 Compute nodes with 2, 4 oder 8 CPU Cores Per core 2 GiByte main memory 2 Infiniband interconnects (MPI- and I/O-Fabric) 68 TByte SAN-Storage Per node 70, 150, 290 GByte scratch- disk OS: SuSE SLES 10 Batch system: LSF Compiler: Pathscale, PGI, Intel, Gnu 3rd party applications: Ansys100, CFX, Fluent, Gaussian, LS-DYNA, Matlab, MSC,…
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AMD Opteron x85 (2,6 GHz) Memory controller on-chip (2 memory channels with 3.2 GiByte/s transfer bandwidth each) Each Core 64 KiByte level 1 instruciton- and data cache 1 MiByte Level 2 Cache 64 Bit extension of IA-32 x86- architecture (x86-64, x64 oder EM64T) Now also as quad core CPUs available
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Instr'n TLB Level 1 Instr'n Cache Fetch 2 - transit Pick Decode 1 Decode 2 Decode 1 Decode 2 Decode 1 Decode 2 Pack Pack Pack Decode Decode Decode 8-entry Scheduler 8-entry Scheduler 8-entry Scheduler ALU AGU ALU AGU ALU AGU FADD FMUL FMISC 36-entry Scheduler Data TLB Level 1 Data Cache ECC 2k Branch Targets 16k History Counter RAS & Target Address Level 2 Cache L2 ECC L2 Tags L2 Tag ECC System Request Queue (SRQ) Cross Bar (XBAR) Memory Controller & HyperTransport
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(4 GiByte)
(Infiniband, Ethernet, Disk)
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(4 GiByte)
(4 GiByte)
(Infiniband, Ethernet, Festplatte)
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(4 GiByte)
(4 GiByte)
(Infiniband, Ethernet, Festplatte)
(4 GiByte)
(4 GiByte)
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+-------------------+ +--------------------+ +-------------------+ | Switch 1 | | Switch 2 | | Switch 3 | | | 30x | | 30x | | | Rack 05 |-------| Rack 20 |-------| Rack 25 | | | | | | | | all Phase1 Nodes | | Phase2 Duals+Quads | | Phase 2 Singles | +-------------------+ +--------------------+ +-------------------+
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24 Port Mellanox 24 Port Mellanox 24 Port Mellanox 24 Port Mellanox 24 Port Mellanox 24 Port Mellanox