Introduction to Computer Science
CSCI 109
Andrew Goodney
Fall 2019
Readings
- St. Amant, Ch. 3
Introduction to Computer Science CSCI 109 Readings St. Amant, Ch. - - PowerPoint PPT Presentation
Introduction to Computer Science CSCI 109 Readings St. Amant, Ch. 3 Andrew Goodney Fall 2019 Lecture 2: Architecture Sept. 9th, 2019 Reminders u Take the survey if you havent already u https://tinyurl.com/y2cot2r5 v Password:
Fall 2019
uTake the survey if you haven’t already
u https://tinyurl.com/y2cot2r5
v Password: CS109Fall2019
uHW #1 out by EoD today. Due 9/23 uQuiz #1 is on 9/16. It will cover material taught
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uThe von Neumann architecture uThe Central Processing Unit (CPU) uStorage uInput and Output
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u What do computers do?
v Math with binary numbers
u So what do we need to build a computer?
v Place to store binary numbers v Way to do math
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u Very generic term u ”Place to store a binary number”
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u “math” we need to do with numbers in memory
v ADD v SUBTRACT v MULTIPLY v DIVIDE v AND,OR,XOR,NOT v Etc…
u Assume we can build a circuit that can do this u Takes numbers represented as digital (electrical) values, produces
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OP2
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bus
u Now we can make instructions… u Instructions are binary numbers that tell the circuit what to
u Select the 1st operand, 2nd operand, destination and function u With a series of such instructions the circuit can perform
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u Instruction Memory
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u Fill instruction memory with desired program u Initialize data memory u Run an instruction (given by program counter)
v Then increment program counter v Run next instruction, increment program counter…
u Some early computers were pretty much just this
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u Separate instruction and data memory is inefficient/inflexible u Von Neumann proposed combined data and instruction
u Also want to support larger and heterogeneous memory
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u Controller + ALU + Registers = CPU
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u Controller + ALU = Central Processing Unit (CPU) u CPU has a small amount of temporary memory within it
v Registers v A special register called the program counter (PC)
u CPU performs the following cycle repeatedly
u Fetch
v Get the next instruction from memory
u Decode
v Send the proper signals from the controller to the ALU and Registers
u Execute
v Let the ALU do its work to produce a result
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u Read an instruction from memory u Direct ALU to do some arithmetic or logic operation u Transfer data from one place to another u Prepare for next instruction to be read u Send a directive to input or output device
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u Perform an arithmetic operation on the contents of
u Perform a logical operation on the contents of registers
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u Faster clock (~GHz on modern computers) u Specialized ALU (e.g., GPU) or more than one ALU u Multiprocessing (more than one CPU) u Streamlining Controller-ALU cooperation (pipelining) u More complex ALU instructions
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u How is storage organized ? u Linear ordering v Each stored item has a an address (which is a number) v To retrieve an item you have to know this number v Retrieval is by address
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u Analogy with office files v Each (physical) file has a number v When a file is needed, you ask for it by number v In the office, files may be stored in shelves, on tables, in
u Storage is modular: as long as the person who wants the file
u Or where they are stored: Files may be stored in a basement
u So latency (time to access) differs
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u Only one item can be stored at one memory location u Random access – all locations in one type of memory
u Storage is hierarchical – add new levels of memory
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Cheaper & larger Faster
Registers RAM (memory) Secondary Storage (Disk Space)
u An aside… u Identifying trade-offs is a fundamental engineering skill u Understanding and balancing trade-offs is part of design process u Not always easy to manage! u Conflicting interests u Speed vs. space is very common tradeoff in CS
v So if you want faster execution you need more memory
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u Volatile: memory is erased when power turned off v Registers, RAM (often called primary storage) u Non-volatile: memory intact when power turned off v Secondary storage (disk) u Booting and ROM (read-only memory) u Cache: small, fast memory between registers and RAM
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u Small (but bigger than registers) u Volatile u Fast (not as fast as registers, but faster than RAM) u What to keep in the cache ? v Things that programs are likely to need in the future v Locality principle:
u Look at what items in memory are being used u Keep items from nearby locations (spatial locality) u Keep items that were recently used (temporal locality)
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u Input: Interrupt-driven
v e.g., Key strokes are slow, CPU treats them like special
u Output: Write to special memory (e.g., video memory)
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Controller ALU I/O Devices (USB, etc)
CPU
Registers & Program Counter
Memory DRAM Disk L2 Cache L3 Cache Boot ROM I/O Controller
Disk controller
On die, but not part of "CPU"
u How to compute? u Develop a series of low-level instructions
v Using the registers and/or main memory for storage v Using only low-level operations made available by the particular CPU
u ”Assembly language”
v Or maybe even machine code (probably not, though)
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u Adding four numbers in C is easy
u Equivalent assembly code
u Which one is better ? Are the two equivalent ?
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u C code
u Assembly code
u Machine code 00000010001100100100000000100000
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u C code
u Assembly code
u Machine code 00000010001100100100000000100000
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u ADD Ri Rj Rk
Add contents of registers Ri and Rj and put result in register Rk
u SUBTRACT Ri Rj Rk
Subtract register Rj from register Ri and put result in register Rk
u AND Ri Rj Rk
Bitwise AND contents of registers Ri, Rj and put result in register Rk
u NOT Ri
Bitwise NOT the contents of register Ri
u OR Ri Rj Rk
Bitwise OR the contents of registers Ri, Rj and put result in register Rk
u SET Ri value
Set register Ri to given value
u SHIFT-LEFT Ri
Shift bits of register Ri left
u SHIFT-RIGHT Ri
Shift bits of register Ri right
u MOVE Ri Rj
Copy contents from register Ri to register Rj
u LOAD Mi Ri
Copy contents of memory location Mi to register Ri
u WRITE Ri Mi
Copy contents of register Ri to memory location Mi
u GOTO Mi
Jump to instruction stored in memory location Mi
u COND_GOTO Ri Rj Mi
If Ri > Rj, jump to instruction stored in memory location Mi
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u Central processing: Connie and Alun u The bus: Buster u Storage (Memory): Mr. Lager u Input and output
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M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END What does this program do?
PC R1 R2 R3 R4 R5 R6 M1 M2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3 M107 6 1 6 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3 M107 6 1 6 3 M108 6 1 6 3
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3 M107 6 1 6 3 M108 6 1 6 3 M109 6 1 6 3 6
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3 M107 6 1 6 3 M108 6 1 6 3 M109 6 1 6 3 6 M110 6 1 6 3 6
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
PC R1 R2 R3 R4 R5 R6 M1 M2 3 M100 3 3 M101 3 3 M102 3 1 3 M103 3 1 3 M104 3 1 3 3 M105 3 1 3 2 3 M106 2 1 3 2 3 M107 2 3 1 3 2 3 M108 2 3 1 3 2 3 M104 2 3 1 5 2 3 M105 2 3 1 5 1 3 M106 1 3 1 5 1 3 M107 1 5 1 5 1 3 M108 1 5 1 5 1 3 M104 1 5 1 6 1 3 M105 1 5 1 6 3 M106 5 1 6 3 M107 6 1 6 3 M108 6 1 6 3 M109 6 1 6 3 6 M110 6 1 6 3 6
M100 LOAD M1 R1 M101 SET R2 0 M102 SET R3 1 M103 SET R6 0 M104 ADD R1 R2 R4 M105 SUB R1 R3 R5 M106 MOVE R5 R1 M107 MOVE R4 R2 M108 COND_GOTO R1 R6 104 M109 WRITE R2 M2 M110 END
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u 8008 – Intel 1971
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u 8080 – Intel 1974
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u 6502 – MOS Tech. (later Commodore)
v Used in Atari 2600, Apple II, many others
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u M68000 – Motorola 1979
v Used in Apple Macintosh, many, many others
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u Intel Core i7 - current
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u https://www.youtube.com/watch?v=g_ZaioqF1B0
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