Introducing the LSE-PC Schematics PCB LSE Summer Week 2015 FPGA - - PowerPoint PPT Presentation

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Introducing the LSE-PC Schematics PCB LSE Summer Week 2015 FPGA - - PowerPoint PPT Presentation

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Introducing the LSE-PC Pierre Surply Introduction Introducing the LSE-PC Schematics PCB LSE Summer Week 2015 FPGA Code execution Pierre Surply Application Conclusion EPITA 2016 July 18, 2015 Pierre Surply (EPITA 2016) Introducing

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Introducing the LSE-PC

LSE Summer Week 2015 Pierre Surply

EPITA 2016

July 18, 2015

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 1 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Introduction

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 2 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

LSE-PC

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 3 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

FPGA - CPU

80386SXLP D0 1 Vss 2 HLDA 3 HOLD 4 Vss 5 NA 6 READY 7 Vcc 8 Vcc 9 Vcc 10 Vss 11 Vss 12 Vss 13 Vss 14 CLK2 15 ADS 16 BLE 17 A1 18 BHE 19 Vcc 21 Vss 22 M/IO 23 D/C 24 W/R 25 LOCK 26 FLT 28 Vcc 32 RESET 33 BUSY 34 Vss 35 ERROR 36 PEREQ 37 NMI 38 Vcc 39 INTR 40 Vss 41 Vcc 42 Vcc 48 Vss 49 Vss 50 A2 51 A3 52 A4 53 A5 54 A6 55 A7 56 Vcc 57 A8 58 A9 59 A10 60 A11 61 A12 62 Vss 63 A13 64 A14 65 A15 66 Vss 67 Vss 68 Vcc 69 A16 70 Vcc 71 A17 72 A18 73 A19 74 A20 75 A21 76 Vss 77 Vss 78 A22 79 A23 80 D15 81 D14 82 D13 83 Vcc 84 Vss 85 D12 86 D11 87 D10 88 D9 89 D8 90 Vcc 91 D7 92 D6 93 D5 94 D4 95 D3 96 Vcc 97 Vss 98 D2 99 D1 100 CPU1 +5V D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 BHE BLE WR DC MIO R21 20k +5V LOCK PEREQ BUSY ERROR ADS HLDA CPU_CLK HOLD INTR NMI RESET FLT EP4CE22E22C7N VCCD_PLL3 1 GNDA3 2 VCCA3 3 GND 4 VCCINT 5 IO/DATA1/ASDO 6 IO 7 FLASH_nCE/nCSO 8 nSTATUS 9 IO 10 IO 11 DCLK 12 IO/DATA0 13 nCONFIG 14 TDI 15 TCK 16 VCCIO1 17 TMS 18 GND 19 TDO 20 nCE 21 GND 22 CLK1 23 CLK2 24 CLK3 25 VCCIO2 26 GND 27 IO 28 VCCINT 29 IO 30 IO 31 IO 32 IO 33 VCCINT 34 VCCA1 35 GNDA1 36 VCCD_PLL1 37 VCCINT 38 IO 39 VCCIO3 40 GND 41 IO 42 IO/PLL1_CLKOUTp 43 IO/PLL1_CLKOUTn 44 VCCINT 45 IO 46 VCCIO3 47 GND 48 IO 49 IO 50 IO 51 CLK15 52 CLK14 53 CLK13 54 CLK12 55 VCCIO4 56 GND 57 IO 58 IO 59 IO 60 VCCINT 61 VCCIO4 62 GND 63 IO 64 IO 65 IO 66 IO 67 IO 68 IO 69 VCCINT 70 IO/PLL4_CLKOUTp 71 IO/PLL4_CLKOUTn 72 VCCD_PLL4 73 GNDA4 74 VCCA4 75 IO 76 IO 77 VCCINT 78 GND 79 IO 80 VCCIO5 81 GND 82 IO 83 VCCINT 84 IO 85 IO/DEV_OE 86 IO/DEV_CLRn 87 CLK7 88 CLK6 89 CLK5 90 CLK4 91 CONF_DONE 92 VCCIO6 93 MSEL0 94 GND 95 MSEL1 96 MSEL2 97 IO/INIT_DONE 98 IO/CRC_ERROR 99 IO 100 IO/nCEO 101 VCCINT 102 IO/CLKUSR 103 IO 104 IO 105 IO 106 VCCA2 107 GNDA2 108 VCCD_PLL2 109 IO 110 IO 111 IO/PLL2_CLKOUTn 112 IO/PLL2_CLKOUTp 113 IO 114 IO 115 VCCINT 116 VCCIO7 117 GND 118 IO 119 IO 120 IO 121 VCCIO7 122 GND 123 VCCINT 124 IO 125 CLK8 126 CLK9 127 CLK10 128 CLK11 129 VCCIO8 130 GND 131 IO/DATA2 132 IO/DATA3 133 VCCINT 134 IO 135 IO 136 IO/DATA5 137 VCCINT 138 VCCIO8 139 GND 140 IO 141 IO 142 IO/PLL3_CLKOUTn 143 IO/PLL3_CLKOUTp 144 FPGA1 VCC1P2:1 VCCD_PLL:1 VCCA:1 +3.3V FPGA_CLK TDI TCK TMS TDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 HLDA HOLD READY READY ADS BLE BHE A1 LOCK RESET NMI INTR NC MSEL0 MSEL1 MSEL2 DATA0 ASDO nCSO DCLK RAMCS LED_TST C48 100n C49 100n C50 100n C51 100n C52 100n C53 100n C54 100n C55 100n C56 100n C57 100n C58 100n +3.3V VCCA:1 VCCD_PLL:1 C59 100n C60 100n C61 100n C62 100n +5V VCC1P2:1 R83 20k +5V RAMWE MIO DC WR UART_RX UART_TX R90 10k R91 10k +3.3V R92 10k +3.3V

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 4 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

CPU

80386SXLP D0

1

Vss

2

HLDA

3

HOLD

4

Vss

5

NA

6

READY

7

Vcc

8

Vcc

9

Vcc

10

Vss

11

Vss

12

Vss

13

Vss

14

CLK2

15

ADS

16

BLE

17

A1

18

BHE

19

Vcc

21

Vss

22

M/IO

23

D/C

24

W/R

25

LOCK

26

FLT

28

Vcc

32

RESET

33

BUSY

34

Vss

35

ERROR

36

PEREQ

37

NMI

38

Vcc

39

INTR

40

Vss

41

Vcc

42

Vcc

48

Vss

49

Vss

50

A2

51

A3

52

A4

53

A5

54

A6

55

A7

56

Vcc

57

A8

58

A9

59

A10

60

A11

61

A12

62

Vss

63

A13

64

A14

65

A15

66

Vss

67

Vss

68

Vcc

69

A16

70

Vcc

71

A17

72

A18

73

A19

74

A20

75

A21

76

Vss

77

Vss

78

A22

79

A23

80

D15

81

D14

82

D13

83

Vcc

84

Vss

85

D12

86

D11

87

D10

88

D9

89

D8

90

Vcc

91

D7

92

D6

93

D5

94

D4

95

D3

96

Vcc

97

Vss

98

D2

99

D1

100

CPU1

+5V

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 BHE BLE WR DC MIO 20k

+5V

LOCK PEREQ BUSY ERROR ADS HLDA CPU_CLK HOLD INTR NMI RESET FLT READY C59 100n C60 100n C61 100n C62 100n

+5V

R83 20k

+5V

NG80386SXLP20: 20MHz 386 SX from 1986

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 5 / 53

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FPGA

EP4CE22E22C7N VCCD_PLL3 1 GNDA3 2 VCCA3 3 GND 4 VCCINT 5 IO/DATA1/ASDO 6 IO 7 FLASH_nCE/nCSO 8 nSTATUS 9 IO 10 IO 11 DCLK 12 IO/DATA0 13 nCONFIG 14 TDI 15 TCK 16 VCCIO1 17 TMS 18 GND 19 TDO 20 nCE 21 GND 22 CLK1 23 CLK2 24 CLK3 25 VCCIO2 26 GND 27 IO 28 VCCINT 29 IO 30 IO 31 IO 32 IO 33 VCCINT 34 VCCA1 35 GNDA1 36 VCCD_PLL1 37 VCCINT 38 IO 39 VCCIO3 40 GND 41 IO 42 IO/PLL1_CLKOUTp 43 IO/PLL1_CLKOUTn 44 VCCINT 45 IO 46 VCCIO3 47 GND 48 IO 49 IO 50 IO 51 CLK15 52 CLK14 53 CLK13 54 CLK12 55 VCCIO4 56 GND 57 IO 58 IO 59 IO 60 VCCINT 61 VCCIO4 62 GND 63 IO 64 IO 65 IO 66 IO 67 IO 68 IO 69 VCCINT 70 IO/PLL4_CLKOUTp 71 IO/PLL4_CLKOUTn 72 VCCD_PLL4 73 GNDA4 74 VCCA4 75 IO 76 IO 77 VCCINT 78 GND 79 IO 80 VCCIO5 81 GND 82 IO 83 VCCINT 84 IO 85 IO/DEV_OE 86 IO/DEV_CLRn 87 CLK7 88 CLK6 89 CLK5 90 CLK4 91 CONF_DONE 92 VCCIO6 93 MSEL0 94 GND 95 MSEL1 96 MSEL2 97 IO/INIT_DONE 98 IO/CRC_ERROR 99 IO 100 IO/nCEO 101 VCCINT 102 IO/CLKUSR 103 IO 104 IO 105 IO 106 VCCA2 107 GNDA2 108 VCCD_PLL2 109 IO 110 IO 111 IO/PLL2_CLKOUTn 112 IO/PLL2_CLKOUTp 113 IO 114 IO 115 VCCINT 116 VCCIO7 117 GND 118 IO 119 IO 120 IO 121 VCCIO7 122 GND 123 VCCINT 124 IO 125 CLK8 126 CLK9 127 CLK10 128 CLK11 129 VCCIO8 130 GND 131 IO/DATA2 132 IO/DATA3 133 VCCINT 134 IO 135 IO 136 IO/DATA5 137 VCCINT 138 VCCIO8 139 GND 140 IO 141 IO 142 IO/PLL3_CLKOUTn 143 IO/PLL3_CLKOUTp 144 FPGA1 VCC1P2:1 VCCD_PLL:1 VCCA:1 +3.3V FPGA_CLK TDI TCK TMS TDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 HLDA HOLD READY ADS BLE BHE A1 LOCK RESET NMI INTR NC MSEL0 MSEL1 MSEL2 DATA0 ASDO nCSO DCLK RAMCS LED_TST RAMWE MIO DC WR UART_RX UART_TX R90 10k R91 10k +3.3V R92 10k +3.3V

Altera Cyclone IV EP4CE22E22C7N EQFP 144 pins 22320 logic elements Released in 2009

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 6 / 53

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5V Device Compatibility

DGG OR DGV PACKAGE (TOP VIEW) NC - No internal connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10

1A1 SW 1B1 1A10 1OE SW 1B10 2A1 SW 2B1 2A10 2OE SW 2B10 2 12 48 13 24 47 46 36 35 25

LOGIC DIAGRAM (POSITIVE LOGIC) Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 7 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

5V Device Compatibility

VCC R2 I I 5.0 V ± 0.25 V Model as R1 5.0-V Device Cyclone Device VCCIO VCCIO 3.0 - 3.4 V ± 0.25 V PCI Clamp B

R1 = VCC IOH VIN = VCCIO + 0.7V R2 = (VCC − VIN) − (R1 × IOH) IOH R2 = 120Ω

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 8 / 53

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Voltage Regulation

MCP1700 GND

1

VIN

2

VOUT

3

U6 2.5V/250mA C31 1u C32 1u R11 121 D1

+3.3V +3.3V

MCP1826 VIN

1

GND

2

VOUT

3

U19 1.2V/1A LD1117A GND

1

VOUT

2

VIN

3

U20 3.3V/1A C39 100n C40 10u C41 4.7u C42 4.7u

+5V

F1 110ohms@100MHz C43 10u USB spec requires <=10uF bypass capacitor POWER ON led VCCA:1 VCC1P2:1 VCCD_PLL:1 USB_D+ USB_D- 1 VCC 2 D- 3 D+ 4 ID 5 GND USB1 USB TP1 TP2 TP3 TP4 TP5

5V: CPU, SRAM 3.3V: FPGA In/Out 2.5V: FPGA Analog PLL 1.2V: FPGA internal logic, Digital PLL

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 9 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

FPGA Configuration

2 3 4 1 5 10 9 8 7 6

JTAG1 NC NC M25P16 S

1

DQ1

2

W

3

Vss

4

DQ0

5

C

6

HOLD

7

Vcc

8

FLASH1

+3.3V +3.3V

R71 10k R72 10k VCCA:1 nCSO R73 10k R74 10k R75 1k TDO TCK TMS TDI VCCA:1 DATA0 DCLK ASDO MSEL0 MSEL1 MSEL2 R76 R77 R78 R79 R80 R81 VCCA:1

M25P16: 16Mbits Serial Flash (SPI) MSEL: Active Serial Programming

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 10 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Static RAM

A4

1

A3

2

A2

3

A1

4

A0

5

CE

6

DQ0

7

DQ1

8

DQ2

9

DQ3

10

Vcc

11

Vss

12

DQ4

13

DQ5

14

DQ6

15

DQ7

16

WE

17

A18

18

A17

19

A16

20

A15

21

A14

22

A13

23

A12

24

A11

25

A10

26

A9

27

A8

28

DQ8

29

DQ9

30

DQ10

31

DQ11

32

Vcc

33

Vss

34

DQ12

35

DQ13

36

DQ14

37

DQ15

38

LB

39

UB

40

OE

41

A7

42

A6

43

A5

44

AS6C8016 RAM1

+5V

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAMWE RAMCS A19-A1 D15-D0 BLE BHE RAMCS

Alliance Memory AS6C8016 Static RAM 512K × 16bits

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 11 / 53

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

USB

R22 121 R23 121 C36 100n C37 4.7u

+5V +5V +3.3V +3.3V

FT230X TXD

1

RTS

2

VccIO

3

RXD

4

GND

5

CTS

6

CBUS2

7

USBDP

8

USBDM

9

3V3OUT

10

RESET

11

Vcc

12

GND

13

CBUS1

14

CBUS0

15

CBUS3

16

FTDI1 R24 27 R25 27 C44 47p C45 47p

+3.3V

C35 100n USB_D- USB_D+

TXLED RXLED

UART_TX UART_RX

FT230: USB/UART bridge

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 12 / 53

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Version 1.0

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 13 / 53

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Soldering

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 14 / 53

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Soldering

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 15 / 53

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Version 1.1

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Version 2.0

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Version 2.0

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Version 2.0

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Version 2.0

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Version 3.0

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Top Layer

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Ground Layer

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Power Layer

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Bottom Layer

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Version 3.0

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Version 3.0

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FPGA Design Overview

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 28 / 53

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Bus Controller

CLK ADS A address1 address2 address3 address4 WR READY D data1 data2 data3 data4

Write cyle Read cyle Write cycle Idle Read cycle

CPU Bridge

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 29 / 53

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Bus Controller

CLK ADS A address1 address2 address3 address4 WR READY D data1 data2 data3 data4

Write cyle Read cyle Write cycle Idle Read cycle

CLK ADS A address1 address2 WR READY D data1 d

Write cyle Read cyle

CPU Bridge

CPU Bridge

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 30 / 53

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Bus Controller

CLK ADS A address1 address2 address3 address4 WR READY D data1 data2 data3 data4

Write cyle Read cyle Write cycle Idle Read cycle

address2 address3 data2 data3

Read cyle Write cycle

CPU Bridge

CLK ADS A WR READY D CPU Bridge

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 31 / 53

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Bus Controller

CLK ADS A address1 address2 address3 address4 WR READY D data1 data2 data3 data4

Write cyle Read cyle Write cycle Idle Read cycle

address3 address4 data3

Write cycle Idle Read cycle

CPU Bridge

CLK ADS A WR READY D CPU Bridge

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 32 / 53

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Bus Controller

T1:

ADS ← 0 A ← Requested address If write cycle, D ← Data to write

T2:

ADS ← 1 If read cycle, Data to read ← D

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Memory Controller

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Memory Controller

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Memory Controller

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Memory Controller

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I/O Controller

in al, 0x10 xor al, 1

  • ut 0x10, al

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Internal RAM layout

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 39 / 53

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Reset

  • rg 0xFFF0

reset: mov ax, 0xF000 mov ds, ax mov ss, ax mov sp, 0xFFF0 jmp 0xF000:0x8000 FFFFF0: 00b8 8ef0 8ed8 bcd0 fff0 00ea 0080 00f0 Reset address CS: F000 IP: + FFF0

  • Reset Address:

FFFFF0

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 40 / 53

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Reset

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Reset

jmp 0xF000, 0x8000

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Reset

jmp 0xF000, 0x8000

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Protected Mode

  • rg 0x8000

startup: lgdt [gdtr] mov eax, cr0

  • r eax, 1

mov cr0, eax mov ax, 0x10 mov ds, ax mov ss, ax ;; ljmp 0x08:0xF8400 dw 0xEA66 dd 0xF8400 dw 0x08 align 16 gdt: ... gdtr: Limit dw gdtr - gdt - 1 Base dd 0xF0000 + gdt

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Application

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Block Diagram

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 46 / 53

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Hold State

Hold:

HOLDA ← 1 A, ADS, WR, DC, D, . . . ← Hi-Z

Pierre Surply (EPITA 2016) Introducing the LSE-PC July 18, 2015 47 / 53

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Breakpoint Handling

mov ax, 0xB800 mov gs, ax mov al, 0x42 mov [gs:0x22], al

CLK ADS WR D 0x42 A 0xB8022 HOLDA HOLD UART_TX 0xB8022 0x42

Write cyle Breakpoint handling

CPU Bridge

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Supervisor Qsys

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Emulated Framebuffer

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

Emulated Framebuffer

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Introducing the LSE-PC Pierre Surply Introduction Schematics PCB FPGA Code execution Application Conclusion

LSE-PC interfaces

JTAG

$ jtagconfig -d 1) USB-Blaster [3-1.2] 020F30DD EP3C25/EP4CE22 (IR=10) Node 08186E00 ROM/RAM/Constant #0 Node 19104600 Nios II #0 Node 18206E00 Serial Flash loader #0 Node 30006E00 SignalTap #0 Design hash D8426D4D2FFCB17E6612

USB

$ lsusb Bus 003 Device 056: ID 0403:6015 Future Technology Devices International, Ltd Bridge(I2C/SPI/UART/FIFO) ... $ ls /dev/ttyUSB* /dev/ttyUSB0

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Q&A

lse-pc.readthedocs.org #lse-pc@irc.rezosup.org Ptishell@irc.rezosup.org surply@lse.epita.fr @Ptishell

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