SLIDE 16 Introduction Requirements and prior work Interface design Implementation in MGSim Results Demonstration Conclusion
Architecture model
Control unit Device information FIFO event queue Direct state access 1 Direct state access 2 Direct state access n Request destination selection read/write request
- source
- addr.
- size
- data(opt.)
addr./size/data for write requests Response generator dest. size read response addr./size for read requests Mux Mux Mux resp. data data info event chunk state data 1 state data 2 state data n
9 11+ 10 Interrupt generator interrupt request interrupt enable/channel pop/clear Microcontroller connected to external device enable device/events device type/event notification fills info fills queue update state update state update state