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Impact of the layout on the electrical characteristics of - - PowerPoint PPT Presentation

Impact of the layout on the electrical characteristics of double-sided silicon 3D sensors fabricated at FBK M. Povoli 1 , 2 A. Bagolini 3 M. Boscardin 3 G.-F. Dalla Betta 1 , 2 G. Giacomini 3 . Mattedi 3 E. Vianello 3 N. Zorzi 3 F 1 Dipartimento


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SLIDE 1

Impact of the layout on the electrical characteristics of double-sided silicon 3D sensors fabricated at FBK

  • M. Povoli1,2
  • A. Bagolini3
  • M. Boscardin3

G.-F. Dalla Betta1,2

  • G. Giacomini3

F . Mattedi3

  • E. Vianello3
  • N. Zorzi3

1Dipartimento di Ingegneria e Scienza dell’Informazione

University of Trento, Italy

2INFN Sezione di Padova

Gruppo Collegato di Trento

3Centro per i Materiali e i Microsistemi

Fondazione Bruno Kessler (FBK), Trento, Italy

8th "Hiroshima" Symposium(HSTD-8) December 05 - 08, 2011

[Work supported by INFN CSN V, projects "TREDI" (2005-2008) and "TRIDEAS" (2009-2011), and INFN CSN I, project ATLAS]

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SLIDE 2

Outline 3D detectors Full 3D and simplified approaches Current status at FBK (short summary) Electrical characterization of 3D test structures with different layouts Available layouts of 3D diodes I-V measurements with variable temperature Selected simulation results for different devices Layout effects on detector capacitance Layout effects on electrical quantities inside the devices Conclusions and outlook

2 / 16 Povoli et al.

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SLIDE 3

3D silicon detectors

Original idea and simplified approaches

[S. Parker et. al. in NIMA 395 (1997), 328] Full 3D

  • 1. Single side process
  • 2. Passing through

columns

  • 3. Active-edge

[E. Vianello et al., NSS11, Paper N10-6] [G. Pellegrini et al., NIMA 592 (2008) 38] Simpilfied approaches

  • 1. Double side processes
  • 2. Passing through columns (FBK),

non-passing through columns (CNM)

  • 3. Slim-edge (FBK), 3D guard ring (CNM)
  • 4. P-spray (FBK), p-stop (CNM)

3 / 16 Povoli et al.

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SLIDE 4

Current status at FBK (short summary)

[E. Vianello et al., NSS11 Conference Record, Paper N10-6]

Considerations ◮ ATLAS07: bad currents and low breakdown (p-spray too high) ◮ ATLAS08: better current (less mechanical stress) still low breakdown ◮ ATLAS09: good currents and higher breakdown (p-spray adjusted) Investigation ◮ Try to gain insight into device behavior using TCAD ◮ Measured p-spray, N+ and P+ profiles ◮ Disentangle the effects of each component of the device ◮ Test performed on 3D diodes (two terminal devices, easy to test)

4 / 16 Povoli et al.

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SLIDE 5

FE-I4 3D diode with Field Plate, Layout details

FRONT BACK

◮ Layout compatible with the ATLAS FE-I4 pixel ◮ Minimum N+ to P+ distance equal to 15µm ◮ WITH Field Plate (LFP = 4µm) ◮ Back side metal and P+ patterned ◮ Simulated cell: 25 × 62.5 × 230µm3

5 / 16 Povoli et al.

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SLIDE 6

Other available 3D diodes FE-I4 3D diode

Similar to the previous FE-I4 diode

N+ columns connected only through metal

Larger N+ to P+ distance

NO Field Plate

CMS 3D diode

Layout compatible with the CMS pixel detector

N+ columns connected only through metal

Minimum N+ to P+ distance equal to 18µm

NO Field Plate

Simulated cell: 50 × 75 × 230µm3

80µm 3D diode

80µm pitch

N+ and metal grid both on front and back sides

Minimum N+ to P+ distance equal to 20µm

WITH Field Plate (LFP = 5µm)

Simulated cell: 40 × 40 × 230µm3 6 / 16 Povoli et al.

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SLIDE 7

IV measurements with variable temperature

IV Curves

1e-08 2e-08 3e-08 4e-08 5e-08 6e-08 7e-08 8e-08 10 20 30 40 50 60 70 80 Currents [A] Reverse voltage [V] I-V 80BIG 35°C 30°C 25°C 20°C 15°C 10°C 5°C 0°C

  • 5°C
  • 10°C
  • 15°C
  • 20°C

1e-08 2e-08 3e-08 4e-08 5e-08 6e-08 7e-08 8e-08 10 20 30 40 50 60 70 80 Currents [A] Reverse voltage [V] I-V FEI4 35°C 30°C 25°C 20°C 15°C 10°C 5°C 0°C

  • 5°C
  • 10°C
  • 15°C
  • 20°C

1e-08 2e-08 3e-08 4e-08 5e-08 6e-08 7e-08 8e-08 10 20 30 40 50 60 70 80 Currents [A] Reverse voltage [V] I-V CMS 35°C 30°C 25°C 20°C 15°C 10°C 5°C 0°C

  • 5°C
  • 10°C
  • 15°C
  • 20°C

1e-08 2e-08 3e-08 4e-08 5e-08 6e-08 7e-08 8e-08 10 20 30 40 50 60 70 80 Currents [A] Reverse voltage [V] I-V FEI4-FP 35°C 30°C 25°C 20°C 15°C 10°C 5°C 0°C

  • 5°C
  • 10°C
  • 15°C
  • 20°C

Setup ◮ Devices coming from wafer W20 of the ATLAS09 batch ◮ Devices were diced and wire bonded on small PCBs ◮ Wire bonding contribution is negligible ◮ Temperature variation between −20◦C and 35◦C inside the climatic chamber ◮ Measurements performed with HP4145 Preliminary results ◮ Each type of device has its own characteristic behavior ◮ Breakdown voltages between 40 and 50V ◮ Different current slope for different devices ◮ More details in the next slide...

7 / 16 Povoli et al.

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SLIDE 8

IV measurements with variable temperature

Breakdown voltage vs. temperature

35 40 45 50 55 60

  • 20
  • 10

10 20 30 40 Breakdown voltage [V] Temperature [°C] VBD= 48.50 mV/°C VBD= 76.82 mV/°C VBD= 50.72 mV/°C VBD= 55.42 mV/°C 80BIG FEI4-FP CMS FEI4

Breakdown voltages ◮ Devices breakdown between 40 and 50V ◮ Linear increase with temperature ◮ The increase is between ∼ 50 and ∼ 80mV/◦C ◮ In agreement with the expectation

[Crowell, C. R. and S. M. Sze, Appl. Phys.

  • Lett. 9, 6 (1966) 242-244.]

8 / 16 Povoli et al.

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SLIDE 9

IV measurements with variable temperature

Purpose

Distinction between thermal generation and avalanche generation Equation I(T) = I(TR)

  • T

TR 2 exp

  • E

2kB

  • 1

TR − 1 T

TR = 293.15◦K

1e-11 1e-10 1e-09 1e-08 1e-07 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Currents [A] 1000/T [°K-1] Arrhenius plot - 80BIG

  • Meas. at 10V
  • Calc. at 10V
  • Meas. at 30V
  • Calc. at 30V

1e-11 1e-10 1e-09 1e-08 1e-07 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Currents [A] 1000/T [°K-1] Arrhenius plot - FEI4

  • Meas. at 10V
  • Calc. at 10V

Meas at 30V

  • Calc. at 30V

1e-11 1e-10 1e-09 1e-08 1e-07 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Currents [A] 1000/T [°K-1] Arrhenius plot - CMS

  • Meas. at 10V
  • Calc. at 10V
  • Meas. at 30V
  • Calc. at 30V

1e-11 1e-10 1e-09 1e-08 1e-07 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Currents [A] 1000/T [°K-1] Arrhenius plot - FEI4-FP

  • Meas. at 10V
  • Calc. at 10V
  • Meas. at 30V
  • Calc. at 30V

Results

The calculation was performed at different bias voltages for all the temperatures considered

Good agreement at low biases (e.g 10V)

Closer to breakdown the agreement is lost (e.g. 30V)

Avalanche generation adds up to Shockley-Read-Hall (SRH) generation

FEI4 diode without field plate seems to show breakdown behavior before the others!! 9 / 16 Povoli et al.

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SLIDE 10

Parameters, models and data extraction

Structure parameters

Thanks to symmetry only 1/4 of elementary cell is simulated

Dimensions depending on the simulated layout

Thickness: 230µm

Measured xide charge: 3 × 1011cm−2

Measured oxide thickness: 1µm

Measured (SIMS) doping profiles for p-spray and N+ and P+ diffusions Models and simulation

Mobility: Doping Dependent, High Field Saturation, E-Field normal

Generation/Recombination: SRH, Avalanche

Bias ramp applied on the P+ electrode from the back side Data analysis

Monitor electrical quantities in different regions of the structure

Understand where the breakdown is occurring

2D slices at different depths

Visualization of the most important quantities for our purpose

1D cut extraction from 2D slices to look at the distribution of the electrical quantities 10 / 16 Povoli et al.

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SLIDE 11

C-V measurements vs. C-V simulations

Only available for 80µm diode (Work in progress)

50 100 150 200 250 300 350 400 10 20 30 40 50 Capacitance [pF] Reverse voltage [V] Only columns Columns and p-spray with N+ diffusion with P+ diffusion Full structure Measured Results

Electrodes contribution: ∼ 71pF (constant)

p-spray causes an increase of ∼ 35pF (basically constant)

P+ diffusion and metal on the back side does not cause much increase

N+ diffusion and metal on the front side cause an increase of ∼ 41pF at a bias voltage of 20V

At higher biases the contribution of front side saturates to a value similar to the one obtained only with electrodes and p-spray (∼ 111pF)

Measured capacitance does not saturate at 40V: more voltage required

Results for other devices available soon

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SLIDE 12

Selected simulation results (summary)

◮ C-V simulations are in good agreement with the measured values and

help us to understand and possibly optimize the devices

◮ I-V simulations were also performed (more details in the next slides) ◮ Good agreement on reverse currents and breakdown voltages ◮ FEI4 simulated current is lower than expected (grid issues? checking...) ◮ CMS diode simulations still running (bigger structure, more points) ◮ Thanks to the simulator is possible to better understand what is

happening inside the devices

Diode type Imeas@10V Isim@10V VBD(meas) VBD(sim) [nA] [nA] [V] [V] 80BIG 6.53 4.39 51 48 FEI4 9.27 4.35 39.5 40 FEI4-FP 5.38 4.77 46 43 CMS 5.22 in progress 40 in progress

12 / 16 Povoli et al.

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SLIDE 13

Selected simulation results - FE-4 diode (VB = −35V) E-field

  • Elec. Potential

1D slices

Electric Field distribution

High field at the N+/p-spray junction on the front side (2.65e5 V/cm)

High field at the N+ column/p-spray junction on the back side (2.48e5 V/cm)

E-field also increases under the front side metal (vertical and horizontal metal connections) Electrostatic potential

P+ column brings the bias voltage directly on the front side p-spray

Back side p-spray is also biased at high voltage

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SLIDE 14

Selected simulation results - FE-4 FP diode (VB = −35V) E-field

  • Elec. Potential

1D slices

Electric Field distribution

High field at the N+/p-spray junction on the front side (2.11e5 V/cm)

High field at the N+ column/p-spray junction on the back side (2.53e5 V/cm)

The field-plate helps in redistributing and lowering the E-field on the front side Electrostatic potential

The field-plate helps depleting part of the p-spray close to the N+ diffusion

The potential of the p-spray now drops on a wider region

Higher breakdown voltage (breakdown probably

  • ccurs on the back side)
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SLIDE 15

Conclusions and outlook

◮ We have studied the electrical behavior of different 3D diodes produced

at FBK and found it consistent with the expectations

◮ I-V measurements allow to find the intrinsic breakdown voltages of the

devices and to highlight differences related to device layout

◮ C-V measurements and simulations showed that for lower operating

voltages also the front and back side surfaces contribute to the overall capacitance of the device

◮ A good agreement was found between measurements and simulations,

confirming that TCAD is a reliable tool for device analysis and design (3D simulation compulsory)

◮ We will apply the same step-by-step procedure to I-V simulation in

  • rder to optimize the sensor layout

◮ This study will then continue with irradiated devices (several 3D diodes

will be irradiated with 800 MeV protons at different fluences at Los Alamos later this month)

15 / 16 Povoli et al.

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SLIDE 16

Thank You!

(...any questions?)

Acknowledgement: We would like to thank all members of the Processing Group within the ATLAS 3D Sensor Collaboration for fruitful discussions