IJTAG: EVOLVING 1149.1 OR OPENING PANDORAS BOX? Bill Eklow Cisco - - PowerPoint PPT Presentation

Slide 1 EBTW 2005, Tallinn, Estonia

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IJTAG: EVOLVING 1149.1 OR OPENING PANDORA’S BOX?

Bill Eklow Cisco Systems, Inc. JTAG

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The Evolution of 1149.1

Released in 1990 to address board interconnect test issues Adapted over time to interface to internal chip test features Problem: Board interconnect and chip test generate different requirements for TAP Consequence: No standardized control over TAP controlled chip test features

Ad-hoc implementations Ad-hoc documentation

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The Scope(s) of IJTAG

Standardized Documentation Standardized Protocol TAP Modifications for better chip test support Chip-centric initiative, more hardware focused vs. SJTAG

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LBIST MBIST (Internal and External) I/O BIST (PRBS, Jitter Test) Process Monitors Voltage Monitors State Dump Built in Logic Analyzer IEEE 1500 Wrapped Cores BUT – No directions on how to access these features

The Ideal ASIC?

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Standardized Documentation

Access information for all necessary data and control registers Required instructions/actions

Initialization Execution Wait time Verification of Results

Described in a way which:

Is simple Is flexible Can be supported by EDA and Boundary-scan tools

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Standardized Protocol

Instruction and Data protocols Action sequencing Pass/Fail and Error reporting Intention is similar to SJTAG –common protocol to promote reuse

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Enhanced TAP Controller

Driven by low cost IC tester companies Allow for at speed ATPG testing Support for high volume data Focus on high bandwidth and streamlined TAP

Ethernet or PCI based TAP (security?) Re-ordering of TAP states to support chip based testing Multiple TMS TAP

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Enhanced TAP Controller

Figure [2]: TAP State Machine That Allows Control of AC & DC Scan

Test Logic Reset

1

Run Test Idle

1

Select Data Register

1

Select Instruct Register

1

Update Data Register

1

Update Instruct Register

1

Capture Data Register

1

Capture Instruct Register

1

Exit 1 Data Register

1

Exit 1 Instruct Register

1

Exit 2 Data Register

1

Exit 2 Instruct Register

1

Pause Data Register

1

Pause Instruct Register

1

Shift Data Register

1

Shift Instruct Register

1

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Enhanced TAP Controller

Figure [3]: TAP State Machine Remapped That Allows Control of AC & DC Scan

Test Logic Reset

1

Run Test Idle

1

Select Data Register

1

Select Instruct Register

1

Update Data Register

1

Update Instruct Register

1

Capture Data Register

1

Capture Instruct Register

1

Last Shift

1

Exit 1 Instruct Register

1

First Shift

1

Exit 2 Instruct Register

1

Sample Data Register

1

Pause Instruct Register

1

Shift Data Register

1

Shift Instruct Register

1

Slide 10 EBTW 2005, Tallinn, Estonia

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Quick Overview of SJTAG

Software based initiative Standardized test vector format and protocol for remote communication Optimize reuse of vectors between Test/ATPG platforms Optimize transfer to and execution of test vectors on remote systems Assumes remote, on-board boundary scan controller