IJTAG: EVOLVING 1149.1 OR OPENING PANDORAS BOX? Bill Eklow Cisco - PowerPoint PPT Presentation

IJTAG: EVOLVING 1149.1 OR OPENING PANDORA’S BOX? Bill Eklow Cisco Systems, Inc. EBTW05 EBTW05 JTAG EBTW 2005, Tallinn, Estonia Slide 1

EBTW05 EBTW05 The Evolution of 1149.1 � Released in 1990 to address board interconnect test issues � Adapted over time to interface to internal chip test features � Problem: Board interconnect and chip test generate different requirements for TAP � Consequence: No standardized control over TAP controlled chip test features � Ad-hoc implementations � Ad-hoc documentation EBTW 2005, Tallinn, Estonia Slide 2

EBTW05 EBTW05 The Scope(s) of IJTAG � Standardized Documentation � Standardized Protocol � TAP Modifications for better chip test support � Chip-centric initiative, more hardware focused vs. SJTAG EBTW 2005, Tallinn, Estonia Slide 3

EBTW05 EBTW05 The Ideal ASIC? � LBIST � MBIST (Internal and External) � I/O BIST (PRBS, Jitter Test) � Process Monitors � Voltage Monitors � State Dump � Built in Logic Analyzer � IEEE 1500 Wrapped Cores � BUT – No directions on how to access these features EBTW 2005, Tallinn, Estonia Slide 4

EBTW05 EBTW05 Standardized Documentation � Access information for all necessary data and control registers � Required instructions/actions � Initialization � Execution � Wait time � Verification of Results � Described in a way which: � Is simple � Is flexible � Can be supported by EDA and Boundary-scan tools EBTW 2005, Tallinn, Estonia Slide 5

EBTW05 EBTW05 Standardized Protocol � Instruction and Data protocols � Action sequencing � Pass/Fail and Error reporting � Intention is similar to SJTAG –common protocol to promote reuse EBTW 2005, Tallinn, Estonia Slide 6

EBTW05 EBTW05 Enhanced TAP Controller � Driven by low cost IC tester companies � Allow for at speed ATPG testing � Support for high volume data � Focus on high bandwidth and streamlined TAP � Ethernet or PCI based TAP (security?) � Re-ordering of TAP states to support chip based testing � Multiple TMS TAP EBTW 2005, Tallinn, Estonia Slide 7

EBTW05 EBTW05 Enhanced TAP Controller 1 Test Logic Reset 0 1 Run 0 Select Select Test Data Instruct 1 1 Idle Register Register 0 0 Capture 0 Capture 0 Data Instruct 1 Register 1 Register 0 0 0 0 Shift 0 Shift 0 Data Instruct Register Register 1 1 Exit 1 1 Exit 1 1 Data Instruct Register Register 0 0 0 0 Pause Pause Data Instruct Register Register 1 1 Exit 2 Exit 2 0 0 Data Instruct Register Register 1 1 Update Update 1 Data Instruct 1 Register Register 0 0 Figure [2]: TAP State Machine That Allows Control of AC & DC Scan EBTW 2005, Tallinn, Estonia Slide 8

EBTW05 EBTW05 Enhanced TAP Controller 1 Test Logic Reset 0 1 0 Run Select Select Test Data Instruct 1 1 Idle Register Register 0 0 Capture Capture Data Instruct 1 1 Register Register 0 0 Shift 0 Shift 0 Data Instruct Register Register 1 1 Last 1 Exit 1 1 Shift Instruct Register 0 0 0 0 Sample Pause Data Instruct Register Register 1 1 First Exit 2 0 0 Shift Instruct Register 1 1 Update Update 1 Data Instruct 1 Register Register 0 0 Figure [3]: TAP State Machine Remapped That EBTW 2005, Tallinn, Estonia Slide 9 Allows Control of AC & DC Scan

EBTW05 EBTW05 Quick Overview of SJTAG � Software based initiative � Standardized test vector format and protocol for remote communication � Optimize reuse of vectors between Test/ATPG platforms � Optimize transfer to and execution of test vectors on remote systems � Assumes remote, on-board boundary scan controller EBTW 2005, Tallinn, Estonia Slide 10