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10/28/11 Self-Timed Circuits Ivan Sutherland Portland State University ivans@cecs.pdx.edu Asynchronous Research Center Portland State University October 2011 Offering freedom from the tyranny of the clock FMCAD tutorial Asynchronous Research

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Offering freedom from the tyranny of the clock

Self-Timed Circuits

Ivan Sutherland Portland State University ivans@cecs.pdx.edu

Asynchronous Research Center

Portland State University

October 2011

October 30, 2011 Slide 2 Asynchronous Research Center FMCAD tutorial

Calibration

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the line above, consider moving closer to the screen

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October 30, 2011 Slide 3 Asynchronous Research Center FMCAD tutorial

About the ARC at Portland State

  • People

> Marly Roncken (ex Philips & Intel) now PSU – CS Dept. > Ivan Sutherland (ex Sun) now PSU – ECE Dept. > Willem Mallon (ex Philips & NXP) now PSU – CS Dept.

  • Sponsorship

> College of Engineering, PSU > Oracle > DARPA > Seeking additional sponsors

October 30, 2011 Slide 4 Asynchronous Research Center FMCAD tutorial

Outline

  • Kinetic Learning Activity (KLA)
  • Pipelines
  • Control protocols
  • Performance & Logical Effort
  • Data formats
  • Gate models

> semi modular versus inertial delay

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October 30, 2011 Slide 5 Asynchronous Research Center FMCAD tutorial

KLA rules

  • Predecessor and successor
  • Use only one hand
  • Pred has object AND you don’t
  • Take from predecessor
  • NEVER PUT to successor

October 30, 2011 Slide 6 Asynchronous Research Center FMCAD tutorial

Pipeline action

  • Conditions for action

> predecessor proffers data > successor has space

  • Three part atomic action:

> copy data > make successor FULL > make predecessor EMPTY

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October 30, 2011 Slide 7 Asynchronous Research Center FMCAD tutorial

Pipeline is:

  • Logic stage “L”
  • Wires “w”
  • w L w L w L w L w L w L w
  • Wires may hold data (or not)

October 30, 2011 Slide 8 Asynchronous Research Center FMCAD tutorial

Control protocols

  • Single wire (GasP)

> HI = data valid = FULL

  • Two wires – four phase

> request HI = data valid > acknowledge HI = data accepted

  • Two wires – two phase NRZ

> differ = data valid = FULL > double data rate (DDR)

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October 30, 2011 Slide 9 Asynchronous Research Center FMCAD tutorial

6-4 GasP circuit

  • Single control wire plus data

> HI is FULL convention > bundled data

> control wire is bidirectional

  • Least logical effort => fastest

> forward latency = 6 > reverse latency = 4

  • Normally opaque data latches

October 30, 2011 Slide 10 Asynchronous Research Center FMCAD tutorial

GasP circuit diagram

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October 30, 2011 Slide 11 Asynchronous Research Center FMCAD tutorial

Charlie box

  • Two wires between stages

> differ = FULL > bundled data > acknowledge after capture

  • Fast in forward direction

> forward = 2 via one latch > reverse = 4 via XOR + latch

  • Normally transparent data latches

October 30, 2011 Slide 12 Asynchronous Research Center FMCAD tutorial

Charlie box circuit diagram

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Pipeline essentials

  • One AND function

> pred FULL and succ EMPTY

  • Data captured in latches or flip flops
  • Some relative timing assumptions
  • Compare with source clocking

October 30, 2011 Slide 14 Asynchronous Research Center FMCAD tutorial

Source and sink clocking

  • Source clocking

> clock moves forward with data

  • Sink clocking

> clock moves back with space

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Canopy graph

  • Throughput versus occupancy

> throughput in items/time: GDI/s > occupancy in items/length

  • Maximum throughput
  • Elastic = variable occupancy

> can insert if not full > can withdraw if not empty

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Throughput vs Occupancy for ring of 11 stages

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October 30, 2011 Slide 17 Asynchronous Research Center FMCAD tutorial

Infinity test

M

  • ut

in0 in1

B

in

  • ut0
  • ut1

M F I F O B F I F O F I F O Demand Merge Data-directed Branch

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Infinity: Throughput vs Occupancy

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Mutual exclusion

  • Two events at “same” time

> which choice doesn’t matter > but choice must be clean

  • Flip flop can hang metastable

> exit is Poisson distributed > may take a long time, but rarely will

  • Asynchronous system can wait

October 30, 2011 Slide 20 Asynchronous Research Center FMCAD tutorial

Continental divide

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Mutual exclusion (Seitz)

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Blend control with data

  • Two wires per bit (like domino)

> LO + LO = invalid > LO + HI = one > HI + LO = zero

  • Plus one acknowledge wire

> four-phase, NRZ, or single track > Fulcrum – four phase 18 FO4 cycle

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October 30, 2011 Slide 23 Asynchronous Research Center FMCAD tutorial

Validation issues

  • Loops in each pipeline stage

> interlocked with AND functions > may not have latches or flip flops > hard to verify with conventional tools

  • Slope and delay model

> slope converges quickly > delay converges if slope is known > not available in conventional tools

October 30, 2011 Slide 24 Asynchronous Research Center FMCAD tutorial

Global state

  • Is an unnecessary fiction
  • Handshakes isolate local actions
  • Transactions are what matters
  • Pipelines are easy to think about

> local transactions tell all > avoid state explosion > painless concurrency

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October 30, 2011 Slide 25 Asynchronous Research Center FMCAD tutorial

Fork and join pipes

  • Fork sends same data both ways
  • Join combines two data inputs
  • Fork and joint parallel pipelines

> storage capacity of the shorter > latency of the slower > slack matching avoids

  • excess storage
  • excess latency

October 30, 2011 Slide 26 Asynchronous Research Center FMCAD tutorial

Unique verification tasks

  • Combinational Loops
  • Slack matching
  • Working with local state
  • Deadlock

> wormhole networks OK if no loops > other cases?

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