HW & SW co-verification of baseband HSPA Processor with Seamless - - PowerPoint PPT Presentation

HW & SW co-verification of baseband HSPA Processor with Seamless PSP

Zheng Li, Xuedong Yang, Bing Wang, Zhitao Lu, Lawrence Yang, James Gualdoni, Jagan Raghavendran Steven Swanchara, William Hinkel, Scott Wincklhofer, Marc Shelton, Raymond Tsui

WOCC2007, NJIT, April 27, 2007

The Structure of UMTS HSPA channels Co-design and co-verification advantages TTT significance with HW/SW co-verification Setup Co-verification environment with Seamless PSP HSPA Baseband Channel processing Explore HDL Link to Vstation for speeding up HW/SW emulation Summary

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Overview

• Structure of the HSPA channels

Uplink :

E-DPDCH (User Info) E-DPCCH (Physical channel , Associated Signaling ) HS-DPCCH (Physical channel , feedback)

Node B

UE

Downlink

HS-DSCH (Physical channel ) HS-SCCH (Physical channel , associated sygnalling ) E-AGCH (Physical Channel , feedback) E-RGCH (Physical Channel , feedback) E-HICH (Physical Channel , feedback)

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• TTT:
• In the early stage of baseband channel card

development of HSPA (High Speed Packet Access) for W-CDMA system, an effective Hardware and Software co-verification platform can help the team to reduce the TTT (Time To Technology) period.

• Cycle-accurate Simulation:
• Co-simulation or co-verification environment (CVE)

with Seamless PSP Simulator and VHDL HW simulator will help the developers to shorten the time for development.

• Benefits to both HW and SW designers

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Co-design and verification advantages

• The configuration and execution of co-verification

tool takes place in a higher abstract level, while the DSP FW and RTL partition can progress in specific lower design level and the executable code will target to the physical board when it’s available.

• Using the Seamless CVE simulator on Unix station,

with the HSPA symbol-level control logic being verified in a DSP simulator, the chip-level signal processing can be verified parallel in a VHDL simulator in the same environment that keeps the design consistency.

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• High level abstract v.s. low level design

• The significance of co-verification

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

Much shorter TTT compared to TTM Closed the Time Gap between HW/SW develop & Sys test. Reduced system integration time.

HW Design SW Design Co- verification TTM TTT

Time Gap

Job done

Board level testing Board level testing Board level testing

• Modulation scheme & HSDPA peak rate

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• QPSK:
• Channel Bit Rate = 480 kbps
• Channel Symbol Rate = 240 ksps
• Bits/HS-DSCH Subframe = 960 bit/subfrm
• Peak Rate = 960 x 15 / 2msec = 7.2 Mbps
• 16 QAM:
• Channel Bit Rate = 960 kbps
• Channel Symbol Rate = 240 ksps
• Bits/HS-DSCH Subframe = 1920 bit/subfrm
• Peak Rate = 1920 x 15 /2ms = 14.4 Mbps

• Explore Peak rate HSDPA system

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

480 mod Sym 480 mod Sym 480 mod Sym 480 mod Sym

16 QAM

SC1 (16 chips) SC2 SC3 SC15

. . . . . .

Symbol Secletion

1920 bits / HS- DSCH subframe

Turbo Coding Information: 27952 bits

Max Transport Block Size

Data Rate = 27952 bits / 2 msec = 13.976 Mbps Basic Coding R = 1/3

83856

code bits

28800

bits 1920 bits / HS- DSCH subframe 1920 bits / HS- DSCH subframe 1920 bits / HS- DSCH subframe 3.84 x 10^6 chip/sec 1 subframe = 2 msec

Effective Coding Rate = 27952 bits / 28800 = 0.97

• Modulation scheme & HSUPA Peak rate

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

C 1,0

C 2,1

C 2,0 C 4,0

C 4,1

C 4,2 C 4,3

Data rate @ SF=4 is 960 kbps Data rate @ SF=2 is 1920 kbps 1920 bits/TTI 3840 bits/TTI

I channel: 3840 + 1920 = 5760 bits Q channel: 3840 + 1920 = 5760 bits

11520 bits/TTI = 5.76 Mbps

per TTI = 2ms

C 8,0 C 8,1 C 8,7 C 8,3 C 8,5

QPSK

• Processor Support Package

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

HW/SW PSP (processor support package) Models in industry for ADI, ARM, IBM, MIPS, StartCore, TI, ZSP, …, processor devices. PSP model simulates most of the pins of the industrial Processor chip device accurately. Seamless CVE model.

• Prepare DSP design and HDL design for

the Seamless PSP and Modelsim

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

DSP FW design HDL SW design Select the proper: Compiler Assmebler Linker DSP executable image For DSP Simulator vlib work: Creating HDL design library Vcom: Compile the design package HDL executable image For HDL ModleSim

• Format conversion to fit the DSP PSP simulator

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

DSP Simulator in Windows CVE: Reloadable Executable file DSP Simulator in UNIX CVE : Reloadable Executable file PSP

Format conversion Format conversion

• HSPA baseband processor co-simulation

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

External SRAM

EMIF P

• r

t mem

Test Vectors Generator

EMIF Bus EDMA Transfer Matchpoint Matchpoint

Interupt Acknowledge

Seamless PSP

• f

DSP processor DSP Simulator: Symbol level processing HDL simulator: Chip level processing

The developed DSP software and HW RTL code will b

re-used on the physical HSPA channel processor card simultaneously or later in the lab or in the field.

• HSPA Baseband processing GUI: Seamless PSP,

DSP debugger and Modelsim

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

Seamless Configuration Define memory mapping for all processors & registers HDL simulator Modelsim invocation DSP Software simulator invocation

• Baseband channel processing

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07 Symbol level Processor Scheduler Chip level Processor

Response Request Data/ control Data/ control Data/ control Data/ control

Rel 99 Channel setup HSPA channel setup HSPA Parameter configuration Reconfiguration Handover Power adjustment Measurement Error monitoring … ...

• Explore Vstation emulation with HDL Link

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

Workstation Simulator VStation Emulator HDL Testbench Design Under Test Transaction Interface Portal co-modeling HDL LINK

HDL Link helps to establish:

• Testbench Only in Software Simulator;
• Testbench and behavioral blocks in Software Simulator;
• Block-by-block migration. Migrate the HDL RTL code

from the workstation Simulator to Vstation Emulator;

• TIP co-modeling enhanced the performance and debug

capabilities.

• Compile the design for HW partitioning

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

VHDL OM units

Partioner

RTLC Partition Database VMW Netlist

igen

Behave Shadow and Gate Netlist RTL Transactors RTLC vmwNetlist Design Database Integration Files Mixnet.info Gate Shadow Hierachy Design Unit

Partition a module in

• Vstation region
• Behave region
• In-Circuit

Emulation region

• below a certain

module

Output: Compiled database used at runtime.

• Vstation with MCT testbench

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

Input Test Vectors Vstation output

Vstation

MCT Testbench

Comparison Mechanism

• Multi-Channel Transport co-modeling enables SW

testbench run HW verification at high speed.

• Transactor portability for ASIC interfaces.
• System level modeling and verification in C/C++, SystemC

• - All signals are visible to user at any time.
• - User can set break-point on Behavioral signal,

change signal without re-compile.

• User can set trigger on Vstation signal to stop

the emulation. …

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Debugging Vstation with HDL Link

depends on:

• ASIC/FPGA Design size
• Vstation Driven Clock
• Simulator on what kind of Workstation
• The number of behavioral blocks still

remained in HDL Link testbench.

• The method used to hook Simulator onto

Emulator

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Vstation Emulation Speed v.s.

Workstation Simulation Speed

• - 3G Rel. 99 baseband processor.
• - 3G Rel. 5 for HSDPA baseband processor
• 3G Rel. 6 for HSUPA baseband processor
• LTE baseband processor
• future wireless & comm. SoC processor

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Design and co-verification Target

• Seamless CVE with application specific PSP provides a

flexible DSP simulator solution to the HSPA baseband processor development that can cycle-accurately simulate the symbol level processing together with the Modelsim chip-level processing.

• HDL link can be considered to use in partitioning the HDL

design modules onto Vstation for high speed emulation.

• System level verification methodologies can close the gap

between the SW design and HW design, and between the sequential processing and parallel processing.

• HSPA verification methodologies introduced here applies to

any large scale DSP, FPGA and ASIC integration system.

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Summary

• [1] 3GPP TS 25.211, TS25.212, TS 25.214 Technical Specification. 3rd

Generation Partnership Project, Technical Specification Group Radio Access Network, FDD Release 5, Release 6.

• [2] HDL Link User’s Guide. Mentor Graphics HDL Link Software, 2004.
• [3] WCDMA for UMTS, Radio Access for Third Generation Mobile
• Communications. By Harri Holma and Antti Toshala.

HW & SW co-verification of baseband HSPA processor with Seamless, wocc07

• Reference
• Contact
• zhengli@alcatel-lucent.com
• zhengli@ieee.org