HW & SW co-verification of baseband HSPA Processor with Seamless PSP Zheng Li, Xuedong Yang, Bing Wang, Zhitao Lu, Lawrence Yang, James Gualdoni, Jagan Raghavendran Steven Swanchara, William Hinkel, Scott Wincklhofer, Marc Shelton, Raymond Tsui WOCC2007, NJIT, April 27, 2007
• Overview � The Structure of UMTS HSPA channels � Co-design and co-verification advantages � TTT significance with HW/SW co-verification � Setup Co-verification environment with Seamless PSP � HSPA Baseband Channel processing � Explore HDL Link to Vstation for speeding up HW/SW emulation � Summary HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Structure of the HSPA channels Downlink HS-DSCH (Physical channel ) HS-SCCH (Physical channel , associated sygnalling ) E-AGCH (Physical Channel , feedback) E-RGCH (Physical Channel , feedback) E-HICH (Physical Channel , feedback) Uplink : E-DPDCH (User Info) E-DPCCH (Physical channel , Associated Signaling ) HS-DPCCH (Physical channel , feedback) UE Node B HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Co-design and verification advantages • TTT: • In the early stage of baseband channel card development of HSPA (High Speed Packet Access) for W-CDMA system, an effective Hardware and Software co-verification platform can help the team to reduce the TTT (Time To Technology) period. • Cycle-accurate Simulation: • Co-simulation or co-verification environment (CVE) with Seamless PSP Simulator and VHDL HW simulator will help the developers to shorten the time for development. • Benefits to both HW and SW designers HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• High level abstract v.s. low level design • The configuration and execution of co-verification tool takes place in a higher abstract level, while the DSP FW and RTL partition can progress in specific lower design level and the executable code will target to the physical board when it’s available. • Using the Seamless CVE simulator on Unix station, with the HSPA symbol-level control logic being verified in a DSP simulator, the chip-level signal processing can be verified parallel in a VHDL simulator in the same environment that keeps the design consistency. HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• The significance of co-verification Time Board Board HW Design Board level testing level level Gap SW Design testing testing Co- verification TTT TTM Job done Much shorter TTT compared to TTM Closed the Time Gap between HW/SW develop & Sys test. Reduced system integration time. HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Modulation scheme & HSDPA peak rate • QPSK: • Channel Bit Rate = 480 kbps • Channel Symbol Rate = 240 ksps • Bits/HS-DSCH Subframe = 960 bit/subfrm • Peak Rate = 960 x 15 / 2msec = 7.2 Mbps • 16 QAM: • Channel Bit Rate = 960 kbps • Channel Symbol Rate = 240 ksps • Bits/HS-DSCH Subframe = 1920 bit/subfrm • Peak Rate = 1920 x 15 /2ms = 14.4 Mbps HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Explore Peak rate HSDPA system SC1 (16 chips) 16 QAM 1920 bits / HS- 480 mod Sym DSCH subframe 3.84 x 10^6 chip/sec 1 subframe = 2 msec SC2 1920 bits / HS- 480 mod Sym Basic Coding DSCH subframe R = 1/3 SC3 Information: 27952 bits 83856 28800 Max Transport code bits bits Block Size Turbo Symbol 1920 bits / HS- 480 mod Sym Coding Secletion DSCH subframe Data Rate . . . . . . = 27952 bits / 2 msec = 13.976 Mbps Effective Coding Rate = 27952 bits / 28800 = 0.97 SC15 1920 bits / HS- 480 mod Sym DSCH subframe HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Modulation scheme & HSUPA Peak rate QPSK C 8,0 C 4,0 C 8,1 C 2,0 Data rate @ SF=4 is 960 kbps 1920 bits/TTI C 4,1 C 8,3 C 1,0 11520 bits/TTI I channel: 3840 + 1920 = 5760 bits = 5.76 Mbps Q channel: 3840 + 1920 = 5760 bits per TTI = 2ms C 4,2 C 8,5 Data rate @ SF=2 is 1920 kbps 3840 bits/TTI C 2,1 C 4,3 C 8,7 HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Processor Support Package HW/SW PSP (processor support package) Models in industry for ADI, ARM, IBM, MIPS, StartCore, TI, ZSP, …, processor devices. PSP model simulates most of the pins of the industrial Processor chip device accurately. Seamless CVE model. HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Prepare DSP design and HDL design for the Seamless PSP and Modelsim DSP FW design HDL SW design vlib work: Select the proper: Creating HDL Compiler design library Assmebler Vcom: Linker Compile the design package DSP executable image HDL executable image For DSP Simulator For HDL ModleSim HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Format conversion to fit the DSP PSP simulator DSP Simulator in Windows CVE: Reloadable Executable file Format conversion PSP Format conversion DSP Simulator in UNIX CVE : Reloadable Executable file HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• HSPA baseband processor co-simulation External SRAM EMIF Bus Interupt EMIF Acknowledge DSP Simulator: Seamless PSP HDL simulator: P Symbol level of Chip level EDMA Transfer o mem processing DSP processor processing r t Matchpoint Matchpoint Test Vectors Generator The developed DSP software and HW RTL code will b re-used on the physical HSPA channel processor card simultaneously or later in the lab or in the field. HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• HSPA Baseband processing GUI: Seamless PSP, DSP debugger and Modelsim Seamless Configuration Define memory mapping for all processors & registers HDL simulator Modelsim invocation DSP Software simulator invocation HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Baseband channel processing Rel 99 Channel setup HSPA channel setup HSPA Parameter configuration Reconfiguration Scheduler Handover Power adjustment Data/ Measurement control Response Error monitoring … Request ... Data/ control Data/ Symbol level Chip level control Processor Processor Data/ control HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Explore Vstation emulation with HDL Link Workstation Simulator VStation Emulator HDL LINK HDL Design Under Transaction Interface Portal Testbench Test co-modeling HDL Link helps to establish: - Testbench Only in Software Simulator; - Testbench and behavioral blocks in Software Simulator; - Block-by-block migration. Migrate the HDL RTL code from the workstation Simulator to Vstation Emulator; - TIP co-modeling enhanced the performance and debug capabilities. HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Compile the design for HW partitioning Design Unit Partition a module in VHDL OM units - Vstation region Partioner - Behave region - In-Circuit Partition Database RTLC Emulation region - below a certain VMW Netlist module igen Output: Compiled Behave Shadow and RTL Transactors Gate Netlist database used at RTLC runtime. vmwNetlist Design Gate Shadow Integration Files Mixnet.info Database Hierachy HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Vstation with MCT testbench Vstation MCT Testbench Input Test Vectors Vstation output Comparison Mechanism - Multi-Channel Transport co-modeling enables SW testbench run HW verification at high speed. - Transactor portability for ASIC interfaces. - System level modeling and verification in C/C++, SystemC HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Debugging Vstation with HDL Link • - All signals are visible to user at any time. • - User can set break-point on Behavioral signal, change signal without re-compile. - User can set trigger on Vstation signal to stop the emulation. … HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Vstation Emulation Speed v.s. Workstation Simulation Speed depends on: - ASIC/FPGA Design size - Vstation Driven Clock - Simulator on what kind of Workstation - The number of behavioral blocks still remained in HDL Link testbench. - The method used to hook Simulator onto Emulator HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
• Design and co-verification Target • - 3G Rel. 99 baseband processor. • - 3G Rel. 5 for HSDPA baseband processor - 3G Rel. 6 for HSUPA baseband processor - LTE baseband processor - future wireless & comm. SoC processor HW & SW co-verification of baseband HSPA processor with Seamless, wocc07
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