HPS, A New Microarchitecture: Rationale and Introduction Yale N. - - PowerPoint PPT Presentation

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HPS, A New Microarchitecture: Rationale and Introduction Yale N. - - PowerPoint PPT Presentation

Jan 02, 2023 216 likes •323 views

HPS, A New Microarchitecture: Rationale and Introduction Yale N. Patt, Wen-mei Hwo, and Michael Shebanow Big Picture Three levels of paralellism Big -- threads Medium -- the compiler Small -- hardware Their focus Myopic,

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SLIDE 1

HPS, A New Microarchitecture: Rationale and Introduction

Yale N. Patt, Wen-mei Hwo, and Michael Shebanow

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SLIDE 2

Big Picture

  • Three levels of paralellism
  • Big -- threads
  • Medium -- the compiler
  • Small -- hardware Their focus
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SLIDE 3

Myopic, fine-grain Dataflow

  • Restrict dataflow execution to an “active

window”

  • Feed it with a VN front end
  • No more resource explosion
  • Less parallelism
  • At the mercy of the branch predictor
  • Need a solution for memory ordering.
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SLIDE 4

Components

  • Merger -- integrate newly decoded

instructions into the dataflow graph

  • Register alias table -- map between logical

register names and result buffer entries

  • Node table -- Instruction scheduler. An

entry for each instruction with ready bits.

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SLIDE 5
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SLIDE 6
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SLIDE 7

Implementing HPS

  • Node tables and register alias table are

CAMs

  • Long wires!
  • Lots of area.
  • Not very scalable.
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SLIDE 8

Memory is hard

  • Problem: Address and/or data are not

known at merge time

  • Solution
  • Build a memory alias table.
  • Insert mappings as address/data become
  • known. Younger ops stall until then.