Outline Design Partitioning MIPS Processor Example Architecture - PDF document

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example David Harris Harvey Mudd College Spring 2004 Outline � Design Partitioning � MIPS Processor Example – Architecture – Microarchitecture – Logic Design – Circuit Design – Physical Design � Fabrication, Packaging, Testing 2: MIPS Processor Example CMOS VLSI Design Slide 2 1

Activity 2 � Sketch a stick diagram for a 4-input NOR gate 2: MIPS Processor Example CMOS VLSI Design Slide 3 Activity 2 � Sketch a stick diagram for a 4-input NOR gate VDD D A B C Y GND 2: MIPS Processor Example CMOS VLSI Design Slide 4 2

Coping w ith Complexity � How to design System-on-Chip? – Many millions (soon billions!) of transistors – Tens to hundreds of engineers � Structured Design � Design Partitioning 2: MIPS Processor Example CMOS VLSI Design Slide 5 Structured Design � Hierarchy : Divide and Conquer – Recursively system into modules � Regularity – Reuse modules wherever possible – Ex: Standard cell library � Modularity : well-formed interfaces – Allows modules to be treated as black boxes � Locality – Physical and temporal 2: MIPS Processor Example CMOS VLSI Design Slide 6 3

Design Partitioning � Architecture : User’s perspective, what does it do? – Instruction set, registers – MIPS, x86, Alpha, PIC, ARM, … � Microarchitecture – Single cycle, multcycle, pipelined, superscalar? � Logic : how are functional blocks constructed – Ripple carry, carry lookahead, carry select adders � Circuit : how are transistors used – Complementary CMOS, pass transistors, domino � Physical : chip layout – Datapaths, memories, random logic 2: MIPS Processor Example CMOS VLSI Design Slide 7 Gajski Y-Chart 2: MIPS Processor Example CMOS VLSI Design Slide 8 4

MIPS Architecture � Example: subset of MIPS processor architecture – Drawn from Patterson & Hennessy � MIPS is a 32-bit architecture with 32 registers – Consider 8-bit subset using 8-bit datapath – Only implement 8 registers ($0 - $7) – $0 hardwired to 00000000 – 8-bit program counter 2: MIPS Processor Example CMOS VLSI Design Slide 9 Instruction Set 2: MIPS Processor Example CMOS VLSI Design Slide 10 5

Instruction Encoding � 32-bit instruction encoding – Requires four cycles to fetch on 8-bit datapath format example encoding 6 5 5 5 5 6 R add $rd, $ra, $rb 0 ra rb rd 0 funct 6 5 5 16 I beq $ra, $rb, imm op ra rb imm 6 26 J j dest op dest 2: MIPS Processor Example CMOS VLSI Design Slide 11 Fibonacci (C) f 0 = 1; f -1 = -1 f n = f n-1 + f n-2 f = 1, 1, 2, 3, 5, 8, 13, … 2: MIPS Processor Example CMOS VLSI Design Slide 12 6

Fibonacci (Assembly) � 1 st statement: n = 8 � How do we translate this to assembly? 2: MIPS Processor Example CMOS VLSI Design Slide 13 Fibonacci (Assembly) 2: MIPS Processor Example CMOS VLSI Design Slide 14 7

Fibonacci (Binary) � 1 st statement: addi $3, $0, 8 � How do we translate this to machine language? – Hint: use instruction encodings below format example encoding 6 5 5 5 5 6 R add $rd, $ra, $rb 0 ra rb rd 0 funct 6 5 5 16 I beq $ra, $rb, imm op ra rb imm 6 26 J j dest op dest 2: MIPS Processor Example CMOS VLSI Design Slide 15 Fibonacci (Binary) � Machine language program 2: MIPS Processor Example CMOS VLSI Design Slide 16 8

MIPS Microarchitecture � Multicycle µ architecture from Patterson & Hennessy PCWriteCond PCSource PCEn PCWrite ALUOp Outputs IorD ALUSrcB MemRead ALUSrcA Control MemWrite RegWrite MemtoReg Op RegDst IRWrite[3:0] [5: 0] 0 M 1 u Jump 6 8 Instruction [5: 0] address x Shift 2 left 2 Instruction [31:26] PC 0 0 Instruction Read M M [25: 21] register 1 u Address u x Read x Instruction Read A Zero 1 Memory data 1 [20: 16] register 2 1 ALU ALU ALUOut MemData 0 Registers result Instruction Write M Read B [15: 0] register Instruction u data 2 0 Write [15: 11] x 1 M Instruction 1 Write data 1 u register data 2 x Instruction 0 3 [7: 0] M u x Memory 1 data ALU register control ALUControl Instruction [5: 0] 2: MIPS Processor Example CMOS VLSI Design Slide 17 Multicycle Controller Instruction fetch 0 1 2 3 Instruction decode/ MemRead MemRead MemRead MemRead register fetch ALUSrcA = 0 ALUSrcA = 0 ALUSrcA = 0 ALUSrcA = 0 IorD = 0 IorD = 0 IorD = 0 IorD = 0 4 IRWrite3 IRWrite2 IRWrite1 IRWrite0 ALUSrcB = 01 ALUSrcB = 01 ALUSrcB = 01 ALUSrcB = 01 ALUSrcA = 0 ALUOp = 00 ALUOp = 00 ALUOp = 00 ALUOp = 00 ALUSrcB = 11 PCWrite PCWrite PCWrite PCWrite ALUOp = 00 PCSource = 00 PCSource = 00 PCSource = 00 PCSource = 00 (Op = 'BEQ') (Op = R-type) (Op = 'J') Reset ' ) Memory address S B ' p = Branch Jump O computation r ( ) o Execution completion B ' completion ' L = O p 5 ( 9 11 12 ALUSrcA = 1 ALUSrcA = 1 ALUSrcA =1 ALUSrcB = 00 PCWrite ALUSrcB = 10 ALUOp = 01 ALUSrcB = 00 PCSource = 10 ALUOp = 00 PCWriteCond ALUOp= 10 PCSource = 01 (Op = 'S B') (Op = 'L B') Memory Memory access access R-type completion 6 8 10 RegDst = 1 MemRead MemWrite RegWrite IorD = 1 IorD = 1 MemtoReg = 0 Write-back step 7 RegDst=0 RegWrite MemtoReg =1 2: MIPS Processor Example CMOS VLSI Design Slide 18 9

Logic Design � Start at top level – Hierarchically decompose MIPS into units � Top-level interface memread 2-phase crystal ph1 memwrite clock oscillator MIPS ph2 8 generator adr processor external 8 writedata reset memory 8 memdata 2: MIPS Processor Example CMOS VLSI Design Slide 19 Block Diagram PCEn PCWriteCond PCSource PCWrite Outputs ALUOp IorD ALUSrcB MemRead ALUSrcA MemWrite Control MemtoReg RegWrite IRWrite[3:0] [5: 0] Op RegDst 0 Jump M u 1 Instruction [5: 0] 6 Shift 8 address x left 2 2 Instruction [31:26] PC 0 0 M u Address Instruction [25: 21] Read register 1 M memwrite x Read u x 1 Memory Instruction [20: 16] Read register 2 data 1 A 1 Zero MemData 0 Registers ALU ALU ALUOut Instruction [15: 0] M Write register Read B result Write Instruction [15: 11] u x data 2 1 M 0 data Instruction register 1 data Write 1 u 2 x Instruction [7: 0] M 0 3 u x memread Memory data 1 register control ALU ALUControl Instruction [5: 0] controller aluop[1:0] alucontrol op[5:0] zero alusrca alusrcb[1:0] pcen pcsource[1:0] memtoreg regdst iord regwrite irwrite[3:0] funct[5:0] alucontrol[2:0] ph1 ph2 reset datapath adr[7:0] writedata[7:0] memdata[7:0] 2: MIPS Processor Example CMOS VLSI Design Slide 20 10

Hierarchical Design mips controller alucontrol datapath standard bitslice zipper cell library alu inv4x flop ramslice or2 fulladder and2 mux4 nor2 inv nand2 mux2 tri 2: MIPS Processor Example CMOS VLSI Design Slide 21 HDLs � Hardware Description Languages – Widely used in logic design – Verilog and VHDL � Describe hardware using code – Document logic functions – Simulate logic before building – Synthesize code into gates and layout • Requires a library of standard cells 2: MIPS Processor Example CMOS VLSI Design Slide 22 11

Verilog Example module fulladder( input a, b, c, a b c output s, cout); a b sum cout c carry s sum s1(a, b, c, s); fulladder cout s carry c1(a, b, c, cout); endmodule module carry( input a, b, c, output cout) assign cout = (a&b) | (a&c) | (b&c); endmodule 2: MIPS Processor Example CMOS VLSI Design Slide 23 Circuit Design � How should logic be implemented? – NANDs and NORs vs. ANDs and ORs? – Fan-in and fan-out? – How wide should transistors be? � These choices affect speed, area, power � Logic synthesis makes these choices for you – Good enough for many applications – Hand-crafted circuits are still better 2: MIPS Processor Example CMOS VLSI Design Slide 24 12

Example: Carry Logic � assign cout = (a&b) | (a&c) | (b&c); Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design Slide 25 Example: Carry Logic � assign cout = (a&b) | (a&c) | (b&c); g1 a x b g2 g4 a y cout c g3 b z c Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design Slide 26 13

Example: Carry Logic � assign cout = (a&b) | (a&c) | (b&c); a p1 b p2 b p4 i4 i3 c p3 a p5 p6 cn cout c n3 a n5 n6 i1 i2 a n1 b n2 b n4 Transistors? Gate Delays? 2: MIPS Processor Example CMOS VLSI Design Slide 27 Gate-level Netlist module carry( input a, b, c, output cout) g1 a x x, y, z; wire b g2 g4 a y cout and g1(x, a, b); c g3 and g2(y, a, c); b z c and g3(z, b, c); g4(cout, x, y, z); or endmodule 2: MIPS Processor Example CMOS VLSI Design Slide 28 14