Hardware-Software Codesign 3. Mapping Applications To Architectures - - PowerPoint PPT Presentation

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Hardware-Software Codesign 3. Mapping Applications To Architectures - - PowerPoint PPT Presentation

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Hardware-Software Codesign 3. Mapping Applications To Architectures Lothar Thiele Computer Engineering Swiss Federal 3 - 1 Institute of Technology and Networks Laboratory System Design specification system synthesis estimation

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3 - 1 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Hardware-Software Codesign

  • 3. Mapping Applications To Architectures

Lothar Thiele

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3 - 2 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

SW-compilation HW-synthesis

System Design

specification system synthesis machine code net lists estimation instruction set intellectual

  • prop. block

intellectual

  • prop. code
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3 - 3 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

What is ahead?

Section 4: Partitioning

  • Some basic methods to assign tasks to computing resources

(or communication to networks and busses).

Section 5: Multiobjective Optimization

  • Generic method to optimize H/S systems (and other

engineering systems)

Section 7: Design Space Exploration

  • Application of these methods to design space exploration
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3 - 4 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

core2 core1 core3

System Synthesis - Mapping

allocation: select components binding: assign functions to components scheduling: determine execution order … finally, synthesis results into implementation

Mapping transforms behavior into structure and execution

mapping partitioning

function_2() function_1() function_3()

channel channel

port port port port write() read()

scheduler

function_2() function_1() function_3() function_2() function_1() function_3()

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3 - 5 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Application Specification

… using an underlying model of computation some examples (see also next slides)

  • task graphs: data flow graph, control flow graph
  • process networks: Kahn process network, synchronous data-flow
  • state machine representations: SpecCharts, StateCharts

[not covered in this course]

for mapping, very often only the process network structure and its (abstract) properties are relevant (abstraction from detailed functionality)

function_2() function_1() function_3() function_2() function_1() function_3() function_2() function_1() function_3()

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3 - 6 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Application Specification - Example 1

x = 3*a + b*b - c; y = a + b*x; z = b - c*(a + b);

+ ∗ ∗ − ∗ + + ∗ −

3 a a a b b b b b c c x y z

data flow graph (DFG)

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3 - 7 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Application Specification - Example 2

Kahn process network

  • example: hierarchical network of MJPEG application
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3 - 8 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Application Specification - Example 3

what_is_this { 1 read(a,b); 2 done = FALSE; 3 repeat { 4 if(a>b) 5 a = a-b; 6 elseif(b>a) 7 b = b-a; 8 else done = TRUE; 9 } until done; 10 write(a); } 1 2 4 6 7 8 9 5 10 done !done

control flow graph (CFG)

read(a,b) done = FALSE repeat until

done

if(a>b)

a=a-b

done=TRUE

done?

write(a)

a>b a<=b

elseif(b>a)

a<b a=b b=b-a

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3 - 9 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Architecture Specification – Example

reflects the structure and (key) properties of the underlying platform … and can be done at different abstraction levels example: system-level architecture specification

  • usually a graph notation is used to describe structure
  • annotations to graph elements reflect properties of the underlying platform,

e.g., processing frequency

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3 - 10 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Mapping Specification - Example

mapping relates application and architecture specifications

  • binds processes to processors
  • binds communication between processes to

communication paths of the architecture

  • specifies resource sharing disciplines and scheduling
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3 - 11 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: DFG Application Model

basic model: data flow graph and static scheduling data flow graph GP(VP, EP)

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3 - 12 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: Architecture Model

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3 - 13 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: Mapping

data flow

application data flow graph GP( , ,EP) architecture graph GA( , ,EA) (all possible) mapping relations EM

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3 - 14 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: Synthesis

Synthesis involves

  • allocation α (subset of VA)
  • binding β (subset of EM), i.e., reflecting the mapping of

application nodes in VP (functional and communication)

  • nto architectural nodes in VA (processors and buses)
  • scheduling τ, i.e., assigning an order among nodes (e.g.,

start time)

  • …and ultimately, implementation of (α, β, τ) targeted to

actual hardware and/or software modules

mapping

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3 - 15 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: … towards Implementation

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3 - 16 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Example: … towards Implementation

V1 5 V2 V3

1 21 29 RISC SB

V6 V7

HWM1

V4

22 30 32 RISC SB HWM1 implementation application &mapping execution schedule

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3 - 17 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Mapping Optimization in the Design Flow

application architecture system-level performance analysis system-level design space exploration loop (typ. automated) search algorithm complete design space exploration loop (typ. manual) hardware/ software synthesis final performance analysis mapping functional validation

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3 - 18 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

Mapping Optimization in the Design Flow

Often based on iterative interaction between optimization and performance analysis Based on quantitative parameters obtained through estimation, e.g., end-to-end delay, throughput, power, temperature

application architecture system-level performance analysis system-level design space exploration loop (typ. automated) search algorithm complete design space exploration loop (typ. manual) hardware/ software synthesis final performance analysis mapping functional validation

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3 - 19 Swiss Federal Institute of Technology Computer Engineering and Networks Laboratory

What is ahead?

Section 4: Partitioning

  • Some basic methods to assign tasks to computing resources

(or communication to networks and busses).

Section 5: Multiobjective Optimization

  • Generic method to optimize H/S systems (and other

engineering systems)

Section 7: Design Space Exploration

  • Application of these methods to design space exploration