Hardware / Software / Analog System Partitioning with SysML and SystemC-AMS Daniela Genius and Ludovic Apvrille daniela.genius@lip6.fr Paris Sorbonne University ERTS 2020
Context and Problematic Basic Concepts Contribution Case Study Conclusion Limitations of MDE for analog/mixed-signal systems ◮ Model-driven approaches are generally limited to digital parts ◮ Virtual prototyping and co-simulation fo cyber-physical systems ◮ Rarely on high abstraction level, before partitioning 2/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Related Work: Virtual Prototyping and Co-Simulation ◮ Modelica/Functional Mockup Interface (Blochwitz et al. 2011) ◮ Ptolemy II (Berkeley 2014) ◮ Metro II (Davare et al. 2007) ◮ Capella/Arcadia (Polarsys) ◮ MARTE with generation for Simics (Taha et al. 2010) ◮ MDGen (SODIUS) ◮ AADL (Feiler et al. 2012) 3/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion HW/SW partitioning and Code generation Functional Simulation and HW/SW Partitioning Verification Hardware Software Design Deployment model Hardware design Hardware Refinements Abstractions VHDL/Verilog Final MPSoC Micro Kernel software Model SystemC- code AMS Virtual Prototype 4/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion SystemC AMS ◮ SystemC-AMS extensions describes an extension of SystemC with AMS and RF features ◮ Different Models of Computation, among them Discrete Event (DE) and Timed Data Flow (TDF) ◮ About to become a standard, new User’s Guide released early january 2020 ◮ Commercialized by Coseda, spin-off of Fraunhofer IIS-EAS Dresden ◮ Co-simulaton between analog (SystemC AMS) and digital (SystemC) parts of the virtual prototype [RAPIDO 2019] 5/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Timed Data Flow (TDF) ◮ Module Timestep ( Tm ): module’s acitvation period ◮ Port Rate ( R ): read or write fixed number of data samples ◮ Port Timestep ( Tp ): period during which each port of a module is activated/time interval between two samples ◮ Port Delay ( D ): store a given number of samples on each activation, read or written on next activation 6/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion TDF Example TDF Cluster A B Y R= 3 R= 2 R= 1 D= 0 D= 1 D= 0 Tp= 2 ms Tp= 2 ms Tp= 4 ms Tm= 6 ms Tm= 4 ms ◮ DE modules: white boxes ◮ TDF modules: gray boxes ◮ Ports: black squares (TDF) white squares (DE) ◮ Converter ports: black and white squares 7/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Modeling and verification approach ◮ Integration of analog aspects into HW/SW partitioning ◮ Represent TDF modules in SysML-like style ◮ DE modules can be directly translated (loops, channel read/write, duration estimation) ◮ Capture behavior of each cluster with UML activity diagram ◮ Representation of analog components in architecture and mapping diagram ◮ Generation of abstract simulation code in C/C++ 8/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Modeling clusters: SysML block diagrams ◮ Blocks connected through ports featuring channels for exchanging data ◮ Control information: events and requests A Y B A_out B_in B_out C_in 9/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Modeling cluster behavior: activity diagrams ◮ Choices directly translated into guarded branch control structures ◮ Cluster Timestep : complexity operator in activity diagram ◮ Estimated or derived from schedule of existing TDF model ◮ Port Rate : number of data samples written to/read from a channel ◮ Behavior of cluster captured within a loop forever 10/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Translation SystemC-AMS Activity Diagram TDF DE void processing(){...} Loop for ever void main_func(){...} Control inside loop operators for(i=0;i<N;i = i+1) for(i=0; i<N; i=i+1){...} exit loop [guard0] [guard1] if(guard0){...} elsif(guard1){} [guard2] else{...} Complexity module.set_timestep(N,unit); N time units operator chan out.write(); out(N) port.set_rate(N); chan in(N) in.read(); Communication port.set_rate(N); operators evt out() out.notify(); evt in.wait(); in() 11/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Simulation and formal verification ◮ Mapping view: analog components are modeled as hardware accelerators ◮ Diagrams are converted into C++ before being simulated or formally verified ◮ Predictive Simulation engine: each processing element advances at its own pace until system event (data transfer, synchronization event, etc.) invalidates current transactions 12/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Case Study: Rover Autonomous vehicle for disaster relief efforts (earthquake) ◮ Telemetric sensors to detect obstacles and navigate terrain autonomously ◮ No obstacles in proximity → decrease sampling rate ◮ Obstacle detected in close proximity → increase sampling rate ◮ Temperature and pressure sensors ◮ Avoid collisions → set time frame → impose maximal latency 13/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Functional view of the rover MainControl DistanceSensor MotorControl changeRate newCommand + calculateTraj : Natural; + calculateCommand : Natural; + samplingRate : Natural; samplingRate + calculateDistance : Natural; + interval : Natural; + change : Boolean; + stateR : Natural; ultrasonicData motorCommand tempData stopTemp startTemp tempData stopTemp startTemp tempData stopTemp startTemp TemperatureSensor + samplingRate : Natural; + sensorOn : Boolean; 14/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Activity Diagrams: Sensors and Motor Control Loop for ever chl ultrasonicData(1) 10 us Loop for ever chl 100 ns chl tempData(1) startT emp(1) chl changeRate(1) chl sensorOn=true stopT emp(1) inside loop [ change==1] [ change==0] [ change==0] Loop 10 times [ change==1] for(i=0;sensorOn;i = i+1) inside loop exit loop exit loop [ ] [ ] interval chl changeRate(1) chl evt stopT emp(1) newCommand() chl chl samplingRate(1) motorCommand(1) sensorOn=false 15/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Activity Diagram: Main Control state 0: obstacles far away state 1: obstacles intermediate distance away state 2: obstacles in close proximity Loop for ever [ stateR==0] [stateR==2 ] [stateR==1 ] chl chl tempData(1) ultrasonicData(1) chl ultrasonicData(1) chl ultrasonicData(1) calculateDistance calculateDistance calculateDistance evt newCommand() evt newCommand() evt chl R R L L? ? newCommand() motorCommand(1) chl motorCommand(1) chl motorCommand(1) chl Depending on the distance, calculate a motor command and new state ultrasonicData(1) [ ] [ ] [ ] [ ] [ ] [ ] stateR=0 [ ] [ ] stateR=2 stateR=2 stateR=0 [ ] stateR=2 stateR=0 stateR=1 chl chl changeRate(1) chl changeRate(1) stateR=1 chl chl stateR=1 stopT emp(1) changeRate(1) changeRate(1) chl chl chl samplingRate(1) samplingRate(1) chl stopT emp(1) chl changeRate(1) chl samplingRate(1) chl samplingRate(1) chl chl chl startT emp(1) startT emp(1) changeRate(1) samplingRate(1) chl samplingRate(1) 16/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Context and Problematic Basic Concepts Contribution Case Study Conclusion Partitioning level architecture and mapping diagram 17/25 31/01/2020 Telecom Paris, Paris Sorbonne University Hw/Sw/Analog System Partitioning
Recommend
More recommend
