Executable Models and Verification from MARTE and SysML: a - - PowerPoint PPT Presentation

▶
executable models and verification from marte and sysml a
SMART_READER_LITE
LIVE PREVIEW

Executable Models and Verification from MARTE and SysML: a - - PowerPoint PPT Presentation

Nov 27, 2023 147 likes •722 views

Introduction SysML MARTE Code Generation Conclusions and Remarks Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities Marcello Mura Amrit Panda Mauro Prevostini

slide-1
SLIDE 1

Introduction SysML MARTE Code Generation Conclusions and Remarks

Executable Models and Verification from MARTE and SysML: a Comparative Study

  • f Code Generation Capabilities

Marcello Mura Amrit Panda Mauro Prevostini marcello.mura@lu.unisi.ch amrit.panda@lu.unisi.ch mauro.prevostini@unisi.ch

ALaRI - University of Lugano

14 March 2008

slide-2
SLIDE 2

Introduction SysML MARTE Code Generation Conclusions and Remarks

Presentation Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-3
SLIDE 3

Introduction SysML MARTE Code Generation Conclusions and Remarks

Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-4
SLIDE 4

Introduction SysML MARTE Code Generation Conclusions and Remarks

Introduction

Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Requirements definition/validation Incremental Design Verification Optimization: Reverse Engineering. Functional evaluation/optimization. Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.

slide-5
SLIDE 5

Introduction SysML MARTE Code Generation Conclusions and Remarks

Introduction

Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Requirements definition/validation Incremental Design Verification Optimization: Reverse Engineering. Functional evaluation/optimization. Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.

slide-6
SLIDE 6

Introduction SysML MARTE Code Generation Conclusions and Remarks

Introduction

Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Requirements definition/validation Incremental Design Verification Optimization: Reverse Engineering. Functional evaluation/optimization. Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.

slide-7
SLIDE 7

Introduction SysML MARTE Code Generation Conclusions and Remarks

Introduction

Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Requirements definition/validation Incremental Design Verification Optimization: Reverse Engineering. Functional evaluation/optimization. Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.

slide-8
SLIDE 8

Introduction SysML MARTE Code Generation Conclusions and Remarks

Introduction

Rationale Automatic generation of code from High Level Modeling Languages helps dealing with the complex systems. Design: Requirements definition/validation Incremental Design Verification Optimization: Reverse Engineering. Functional evaluation/optimization. Evaluation of non functional properties. Proposal Use of the expressiveness of multiple UML2 profiles to improve code generation.

slide-9
SLIDE 9

Introduction SysML MARTE Code Generation Conclusions and Remarks

Modelling Language

UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.

slide-10
SLIDE 10

Introduction SysML MARTE Code Generation Conclusions and Remarks

Modelling Language

UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.

slide-11
SLIDE 11

Introduction SysML MARTE Code Generation Conclusions and Remarks

Modelling Language

UML2 Adds new capabilities, achieves greater semantic accuracy and gives better support for code generation. Model Driven Architecture Defines a framework for Code Generation. Platform independent model are initially defined and then such models are refined for the particular platform. Profiles Means of tailoring UML for particular purposes. Extensions of the language can be inserted.

slide-12
SLIDE 12

Introduction SysML MARTE Code Generation Conclusions and Remarks

Target Languages

SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.

slide-13
SLIDE 13

Introduction SysML MARTE Code Generation Conclusions and Remarks

Target Languages

SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.

slide-14
SLIDE 14

Introduction SysML MARTE Code Generation Conclusions and Remarks

Target Languages

SystemC Represents a flexible choice. SystemC can be used from early design phases down to the implementation phase. Promela Is used for verification through the SPIN Model checker Other Possibilities VHDL, Verilog or similar languages can be used as target languages when HW systems are designed.

slide-15
SLIDE 15

Introduction SysML MARTE Code Generation Conclusions and Remarks

Code generation from Design Languages

Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance

slide-16
SLIDE 16

Introduction SysML MARTE Code Generation Conclusions and Remarks

Code generation from Design Languages

Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance

slide-17
SLIDE 17

Introduction SysML MARTE Code Generation Conclusions and Remarks

Code generation from Design Languages

Commercial solutions Statemate by I-Logix StateFlow by Mathworks (part of Simulink) Research Efforts Generation of test cases. Behavioral Models. RTL and Synthesizable models UML definition of SystemC model Concerns Expressiveness and Performance

slide-18
SLIDE 18

Introduction SysML MARTE Code Generation Conclusions and Remarks

Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-19
SLIDE 19

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML Profile

Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.

slide-20
SLIDE 20

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML Profile

Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.

slide-21
SLIDE 21

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML Profile

Rationale SysML is a graphical modeling language for specifying, analyzing, designing and verifying complex system. Internals SysML contains diagrams that are part of UML2, modified diagrams from UML2 and new diagrams. Scope SysML is particularly adapt for modeling HW/SW systems and aims at extending applicability of UML language to such context.

slide-22
SLIDE 22

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML Profile

slide-23
SLIDE 23

Introduction SysML MARTE Code Generation Conclusions and Remarks

Block Definition Diagrams

Blocks are basic structural elements used to specify hierarchies and interconnections. BDDs describe the relationships between blocks.

bdd System

<> <> << block >> << block >> SoC1

parts module1 module2 flow ports inout flowPort_3

SoC2

slide-24
SLIDE 24

Introduction SysML MARTE Code Generation Conclusions and Remarks

Block Definition Diagrams

bdd SoC1_Structure

<< block >> SoC1

parts module1 module2 flow ports inout flowPort_3

<< block >> module1

values value_1 flow ports

  • ut flowPort_1: type

in flowPort_2: type module1

<< block >>

values value_2 flow ports in flowPort_1: type

  • ut flowPort_2: type

inout flowPort_3: type module2

module2

slide-25
SLIDE 25

Introduction SysML MARTE Code Generation Conclusions and Remarks

Internal Block Diagrams

Describes the internal structure of a block specifying its interconnections.

<> <>

ibd SoC1

module2 module1

flowPort_1 flowPort_2 flowPort_3

slide-26
SLIDE 26

Introduction SysML MARTE Code Generation Conclusions and Remarks

Activity Diagrams

Used to specify the flow of input/outputs and control.

ibd SensorNode RF CPU Sensor Actuator Memory <> <> <> <> <> <>

act SensorNodeActivity [Activity Diagram] a1: Measure a2: Elaborate a4: Store a6: Idle a3: PerformAction a5: Send

[ThresholdOverflown ] [else] [MemoryFull] [else]

slide-27
SLIDE 27

Introduction SysML MARTE Code Generation Conclusions and Remarks

Activity Diagrams

act SensorNodeActivity [Allocation Diagram ] a1: Measure a2: Elaborate a4: Store a6: Idle a3: PerformAction a5: Send

[ThresholdOverflown] [else] [MemoryFull] allocatedTo <<block>>SensorNode.Sensor allocatedTo <<block>>SensorNode.CPU allocatedTo <<block>>SensorNode.Actuator allocatedTo <<block>>SensorNode.RF [else]

slide-28
SLIDE 28

Introduction SysML MARTE Code Generation Conclusions and Remarks

Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-29
SLIDE 29

Introduction SysML MARTE Code Generation Conclusions and Remarks

General Remarks

MARTE Fundamental tool in the design of Real Time Embedded

  • Systems. Both modeling and analysis concerns are tackled.

Semantic Richness Not all the profile can be used for code generation. Expressiveness of the target language may not be sufficient. Complementarity with SysML SysML does not have any particular mean to define timing issues while MARTE is particularly adapt for modeling such aspects.

slide-30
SLIDE 30

Introduction SysML MARTE Code Generation Conclusions and Remarks

General Remarks

MARTE Fundamental tool in the design of Real Time Embedded

  • Systems. Both modeling and analysis concerns are tackled.

Semantic Richness Not all the profile can be used for code generation. Expressiveness of the target language may not be sufficient. Complementarity with SysML SysML does not have any particular mean to define timing issues while MARTE is particularly adapt for modeling such aspects.

slide-31
SLIDE 31

Introduction SysML MARTE Code Generation Conclusions and Remarks

General Remarks

MARTE Fundamental tool in the design of Real Time Embedded

  • Systems. Both modeling and analysis concerns are tackled.

Semantic Richness Not all the profile can be used for code generation. Expressiveness of the target language may not be sufficient. Complementarity with SysML SysML does not have any particular mean to define timing issues while MARTE is particularly adapt for modeling such aspects.

slide-32
SLIDE 32

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE Profile

slide-33
SLIDE 33

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE Profile

slide-34
SLIDE 34

Introduction SysML MARTE Code Generation Conclusions and Remarks

Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-35
SLIDE 35

Introduction SysML MARTE Code Generation Conclusions and Remarks

Framework

Customizable Structure Compiler-like approach to enable framework expansion

slide-36
SLIDE 36

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML

Static Information Mapping SysML structures can be mapped to SystemC in the following way: Parts are mapped to modules. Flow Ports are mapped to ports Allocations are mapped to processes Behavioral Information Mapping State Diagrams are translated into SystemC processes source code.

slide-37
SLIDE 37

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML

Static Information Mapping SysML structures can be mapped to SystemC in the following way: Parts are mapped to modules. Flow Ports are mapped to ports Allocations are mapped to processes Behavioral Information Mapping State Diagrams are translated into SystemC processes source code.

slide-38
SLIDE 38

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML

Static Information Mapping SysML structures can be mapped to SystemC in the following way: Parts are mapped to modules. Flow Ports are mapped to ports Allocations are mapped to processes Behavioral Information Mapping State Diagrams are translated into SystemC processes source code.

slide-39
SLIDE 39

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML

Static Information Mapping SysML structures can be mapped to SystemC in the following way: Parts are mapped to modules. Flow Ports are mapped to ports Allocations are mapped to processes Behavioral Information Mapping State Diagrams are translated into SystemC processes source code.

slide-40
SLIDE 40

Introduction SysML MARTE Code Generation Conclusions and Remarks

SysML

Static Information Mapping SysML structures can be mapped to SystemC in the following way: Parts are mapped to modules. Flow Ports are mapped to ports Allocations are mapped to processes Behavioral Information Mapping State Diagrams are translated into SystemC processes source code.

slide-41
SLIDE 41

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE

Timing Issues Chronometric Time Model: Implicit in the simulation engine. Discrete Time: Can be mapped through SystemC clocks. Dense Time: Is not mappable to SystemC. Clocks All the parameters for a clock object can be expressed through MARTE profile. sc time units (e.g. SC PS, SC NS etc) mapping is straightforward.

slide-42
SLIDE 42

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE

Timing Issues Chronometric Time Model: Implicit in the simulation engine. Discrete Time: Can be mapped through SystemC clocks. Dense Time: Is not mappable to SystemC. Clocks All the parameters for a clock object can be expressed through MARTE profile. sc time units (e.g. SC PS, SC NS etc) mapping is straightforward.

slide-43
SLIDE 43

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE

Timing Issues Chronometric Time Model: Implicit in the simulation engine. Discrete Time: Can be mapped through SystemC clocks. Dense Time: Is not mappable to SystemC. Clocks All the parameters for a clock object can be expressed through MARTE profile. sc time units (e.g. SC PS, SC NS etc) mapping is straightforward.

slide-44
SLIDE 44

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE

Timing Issues Chronometric Time Model: Implicit in the simulation engine. Discrete Time: Can be mapped through SystemC clocks. Dense Time: Is not mappable to SystemC. Clocks All the parameters for a clock object can be expressed through MARTE profile. sc time units (e.g. SC PS, SC NS etc) mapping is straightforward.

slide-45
SLIDE 45

Introduction SysML MARTE Code Generation Conclusions and Remarks

MARTE

Timing Issues Chronometric Time Model: Implicit in the simulation engine. Discrete Time: Can be mapped through SystemC clocks. Dense Time: Is not mappable to SystemC. Clocks All the parameters for a clock object can be expressed through MARTE profile. sc time units (e.g. SC PS, SC NS etc) mapping is straightforward.

slide-46
SLIDE 46

Introduction SysML MARTE Code Generation Conclusions and Remarks

Outline

1

Introduction

2

SysML

3

MARTE

4

Code Generation

5

Conclusions and Remarks

slide-47
SLIDE 47

Introduction SysML MARTE Code Generation Conclusions and Remarks

Case Study

ibd SensorNode RF CPU Sensor Actuator Memory <> <> <> <> <> <>

dataExchange data dataStored actionDecided action measuredTemp extTemp

slide-48
SLIDE 48

Introduction SysML MARTE Code Generation Conclusions and Remarks

Case Study

SC MODULE(CPU) { public sc in <float> measuredTemp : Temperature ; sc inout <float> data : Info ; sc inout <float> dataStored : Info ; sc out <bool> actionDecided : Impulse ; SC CTOR(CPU) { SC THREAD( elaborate ) ; SC THREAD( store ) ; } void elaborate ( ) void store ( ) }; SC MODULE( Sensor ) { public sc in <float> extTemp : Temperature ; sc out <float> measuredTemp : Temperature ; SC CTOR( Sensor ) { SC THREAD( measure ) ; } void measure ( ) };

slide-49
SLIDE 49

Introduction SysML MARTE Code Generation Conclusions and Remarks

Case Study

SC MODULE( Actuator ) { public sc in <bool> actionDecided : Impulse ; sc out <bool> action : Impulse ; SC CTOR( Actuator ) { SC THREAD( performAction ) ; } void performAction ( ) }; SC MODULE(RF) { public sc inout <float> dataExchange : Info ; sc inout <float> data : Info ; SC CTOR(RF) { SC THREAD( send ) ; } void send ( ) };

slide-50
SLIDE 50

Introduction SysML MARTE Code Generation Conclusions and Remarks

Case Study

sc clock(clk1,10,SC NS,0.5)

slide-51
SLIDE 51

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.

slide-52
SLIDE 52

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.

slide-53
SLIDE 53

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.

slide-54
SLIDE 54

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.

slide-55
SLIDE 55

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.

slide-56
SLIDE 56

Introduction SysML MARTE Code Generation Conclusions and Remarks

Conclusions

Conclusions The use of multiple UML profiles can improve code generation phase. MARTE can complement SysML models with timing information. Drawbacks Tool support for MARTE is to be improved. Structured documentation (i.e. book) would be beneficial. Future Work Refinement of the SystemC Mapping. Mapping to Promela/SPIN.