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Generating Heterogeneous Executable Specifications in SystemC from UML/MARTE Models Authors: P.Peil J.Medina H.Posadas E.Villar Slide 1 Index Motivation


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Generating Heterogeneous Executable Specifications in SystemC from UML/MARTE Models

Authors: P.Peñil J.Medina H.Posadas E.Villar

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Index

  • Motivation
  • Design Flow
  • UML/MARTE Methodology
  • Application Examples
  • Conclusions
  • Future Work
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Motivation

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Motivation (1)

MARTE

Generic Resource

SystemC

?

Co-Design ForSyDe MARTE provides semantics to UML Select a subset of MARTE Relate UML/MARTE to SystemC SystemC enables a link to Co-Design Formal Support

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Motivation (2)

  • Massive Concurrency

– Data Dependencies – Relations

  • Characteristic of the interactions

– Formal Semantics – Univocal Description

  • Models of Computation & Communication

(MoCCs)

– Behaviors Semantics Heterogeneity

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Design Flow Proposed

SystemC/HetSC Code Generation

Co-Design

SW HW

System Specification MoCC Analysis System Model

UML/MARTE

Executable Specification

System Simulation

SystemC/ HetSC

refinement

ForSyDe Formal Support

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Formal System Design

  • ForSyDe formal metamodel

– Process – Signals

  • Separation Communication-Computation

– MoCC generic characteristics

  • Untimed MoCs

– No time information – Causality (cause and effects)

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HetSC

  • Methodology for the specification of

concurrent Heterogeneous embedded systems in SystemC

  • Clearly Separation between

Communication and Computation

  • Partitioning Decision not yet taken
  • MoCC Semantics
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UML/MARTE Methodology

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UML/MARTE SystemC Interoperability

  • Hierarchy
  • Computation
  • communication
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Hierarchy

«Component» Element1 «FlowPort» port1_1 «FlowPort» port2_1 «Component» Element2 «FlowPort» port2_2 «FlowPort» port1_2 «Component» Element3 «FlowPort» «Component» Element4 «FlowPort»

sc_module sc_port <<Component>> FlowPort

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Computation

<<ConcurrencyResource>>

«Component» Element1 «ConcurrencyResource» CR1 «FlowPort» «FlowPort» «ConcurrencyResource» CR2 «FlowPort» «FlowPort» «FlowPort» port2_1 «FlowPort» port1_1

Sc_thread

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Communication(1)

«Component» Element1 «FlowPort» port1_1 «FlowPort» port2_1 «Component» Element2 «FlowPort» port2_2 «FlowPort» port1_2 «Component» Element3 «FlowPort» «Component» Element4 «FlowPort» «CommunicationMedia» «CommunicationMedia» «CommunicationMedia»

<<CommunicationMedia>>

«Component» Element1 «ConcurrencyResource» CR1 «FlowPort» «FlowPort» «ConcurrencyResource» CR2 «FlowPort» «FlowPort» «FlowPort» port1_1 «FlowPort» port2_1 «CommunicationMedia» channel

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Communication (2)

<<CommunicationMedia>> <<Flowports>> Provided Interface <<CommunicationEndPoint>> Method <<RtService>>

<<FlowPort>> <<FlowPort>> <<CommunicationEndPoint>> <<CommunicationEndPoint>> <<RtService>> send <<RtService>> receive

… …

SystemC channels

User Channels Predefined Channels

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Application Examples

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Kahn process network(1)

  • Asynchronous communication

– Buffering capacity is required

  • <<StorageResource>>

– resMult

<<FlowPort>> direction = in <<CommunicationEndPoint>> <<RtService>> send synchKind = Asynchronous <<FlowPort>> direction = out <<CommunicationEndPoint>> <<RtService>> receive synchKind = Synchronous

<<CommunicationMedia>> <<StorageResource>> transmMode = simplex

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Kahn process network(2)

  • HetSC channel:

– uc_inf_fifo and uc_fifo

// instances channels channel_1=new uc_fifo<dataType>(“Name, N”) channel_1=new uc_inf_fifo<dataType>(“Name”) // module channels uc_fifo *channel_1; uc_inf_fifo *channel_1

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Synchronous Data Flow(1)

  • Producer rate (P):

– Data written in the channel

  • Consumer rate (C):

– Data to trigger consumption – Number of data consumed

<<FlowPort>> direction = out <<CommunicationEndPoint>> <<RtService>> receive synchKind = synchronous

packetSize = P·elementSize

<<FlowPort>> direction = in <<CommunicationEndPoint>> <<RtService>> send synchKind = Asynchronous

packetSize = C·elementSize

<<CommunicationMedia>> <<StorageResource>> transmMode = simplex elementSize resMult = C

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Synchronous Data Flow(3)

  • HetSC channel:

– uc_arc_seq

uc_arc_seq *channel1;

channel1=new uc_arc_seq <dataType, production_rate, consumption_rate>(“Name”);

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Conclusions

  • Interoperability between SystemC and the

system level modeling with MARTE

– supported by formal bases

  • Generation executable Specifications from

UML/MARTE models Identify different MoCCs in MARTE and SystemC

  • Automatic Transformation
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Future Work

  • Synchronous MoC

– Synchronous Reactive – Clocked Synchronous

  • Functionality Description

– Activity Diagram combined with Time Modeling and CCSL

  • Automatic Generation