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Generating Heterogeneous Executable Specifications in SystemC from UML/MARTE Models Authors: P.Peil J.Medina H.Posadas E.Villar Slide 1 Index Motivation


  1. Generating Heterogeneous Executable Specifications in SystemC from UML/MARTE Models Authors: P.Peñil J.Medina H.Posadas E.Villar Slide 1 ��������������������������

  2. Index • Motivation • Design Flow • UML/MARTE Methodology • Application Examples • Conclusions • Future Work Slide 2 ��������������������������

  3. Motivation Slide 3 ��������������������������

  4. Motivation (1) MARTE provides MARTE semantics to UML Select a subset of MARTE Generic Resource ForSyDe ? Relate UML/MARTE to SystemC Formal Support SystemC SystemC enables a Co-Design link to Co-Design Slide 4 ��������������������������

  5. Motivation (2) • Massive Concurrency – Data Dependencies – Relations • Characteristic of the interactions – Formal Semantics – Univocal Description • Models of Computation & Communication (MoCCs) – Behaviors Semantics Heterogeneity Slide 5 ��������������������������

  6. Design Flow Proposed System Specification System Model UML/MARTE MoCC Formal Support SystemC/HetSC Analysis Code Generation ForSyDe Executable refinement SystemC/ Specification HetSC System Simulation Co-Design SW HW Slide 6 ��������������������������

  7. For mal Sy stem De sign • ForSyDe formal metamodel – Process – Signals • Separation Communication-Computation – MoCC generic characteristics • Untimed MoCs – No time information – Causality (cause and effects) Slide 7 ��������������������������

  8. HetSC • Methodology for the specification of concurrent Het erogeneous embedded systems in S ystem C • Clearly Separation between Communication and Computation • Partitioning Decision not yet taken • MoCC Semantics Slide 8 ��������������������������

  9. UML/MARTE Methodology Slide 9 ��������������������������

  10. UML/MARTE SystemC Interoperability • Hierarchy • Computation • communication Slide 10 ��������������������������

  11. Hierarchy «Component» «Component» «FlowPort» Element1 Element3 «FlowPort» port1_1 «FlowPort» «FlowPort» port2_1 port2_2 «Component» «Component» «FlowPort» Element2 «FlowPort» Element4 port1_2 <<Component>> FlowPort sc_module sc_port Slide 11 ��������������������������

  12. Computation <<ConcurrencyResource>> «Component» Element1 «FlowPort» «FlowPort» «FlowPort» «ConcurrencyResource» «ConcurrencyResource» «FlowPort» CR1 CR2 «FlowPort» «FlowPort» port1_1 port2_1 Sc_thread Slide 12 ��������������������������

  13. Communication(1) «Component» «Component» «FlowPort» Element1 «FlowPort» Element3 port1_1 «CommunicationMedia» «FlowPort» port2_1 <<CommunicationMedia>> «CommunicationMedia» «Component» «FlowPort» «FlowPort» Element4 port2_2 «Component» «FlowPort» Element2 port1_2 «CommunicationMedia» «Component» Element1 «FlowPort» «FlowPort» «FlowPort» port1_1 «FlowPort» «ConcurrencyResource» «ConcurrencyResource» CR2 «FlowPort» CR1 «CommunicationMedia» «FlowPort» port2_1 channel Slide 13 ��������������������������

  14. Communication (2) <<CommunicationEndPoint>> <<RtService>> receive <<Flowports>> <<FlowPort>> … <<CommunicationMedia>> Provided Interface … <<CommunicationEndPoint>> <<FlowPort>> <<RtService>> send Method <<CommunicationEndPoint>> <<RtService>> User Channels SystemC channels Predefined Channels Slide 14 ��������������������������

  15. Application Examples Slide 15 ��������������������������

  16. Kahn process network(1) • Asynchronous communication <<CommunicationEndPoint>> – Buffering capacity is required <<RtService>> receive <<FlowPort>> synchKind = Synchronous direction = out • <<StorageResource>> – resMult <<CommunicationMedia>> transmMode = simplex <<StorageResource>> <<FlowPort>> direction = in <<RtService>> send synchKind = Asynchronous <<CommunicationEndPoint>> Slide 16 ��������������������������

  17. Kahn process network(2) • HetSC channel: – uc_inf_fifo and uc_fifo // module channels uc_fifo *channel_1; uc_inf_fifo *channel_1 // instances channels channel_1=new uc_fifo <dataType>(“Name, N”) channel_1=new uc_inf_fifo <dataType>(“Name”) Slide 17 ��������������������������

  18. Synchronous Data Flow(1) <<CommunicationEndPoint>> packetSize = P·elementSize • Producer rate (P) : – Data written in the channel <<RtService>> receive <<FlowPort>> synchKind = synchronous direction = out • Consumer rate (C) : – Data to trigger consumption <<CommunicationMedia>> transmMode = simplex – Number of data consumed elementSize <<StorageResource>> resMult = C <<FlowPort>> direction = in <<RtService>> send synchKind = Asynchronous packetSize = C·elementSize <<CommunicationEndPoint>> Slide 18 ��������������������������

  19. Synchronous Data Flow(3) • HetSC channel: – uc_arc_seq uc_arc_seq *channel1; channel1=new uc_arc_seq <dataType, production_rate , consumption_rate >(“Name”); Slide 19 ��������������������������

  20. Conclusions • Interoperability between SystemC and the system level modeling with MARTE – supported by formal bases • Generation executable Specifications from UML/MARTE models Identify different MoCCs in MARTE and SystemC • Automatic Transformation Slide 20 ��������������������������

  21. Future Work • Synchronous MoC – Synchronous Reactive – Clocked Synchronous • Functionality Description – Activity Diagram combined with Time Modeling and CCSL • Automatic Generation Slide 21 ��������������������������

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