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Hardware Description Languages VHDL 1 benyamin@mehr.sharif.edu - - PowerPoint PPT Presentation

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Hardware Description Languages VHDL 1 benyamin@mehr.sharif.edu Midterm 25% Final 35% Homework and Quiz 20% Project 20% Reference: Zain Navabi, VHDL, analysis and modeling of digital

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Hardware Description Languages

VHDL

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  • Midterm

25%

  • Final

35%

  • Homework and Quiz 20%
  • Project

20%

  • Reference:

– Zain Navabi, ”VHDL, analysis and modeling of digital systems”,McGraw-Hill,2nd Edition, 1998

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Chapter 1 Hardware Design Environment

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Digital System Design Process

Design Idea Behavioral Design Data Path Design Logic Design Physical Design Manufacturing Chip or Board Flow Graph, Pseudo Code Bus & Register Structure Gate Wirelist, Netlist Transistor List, Layout

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Design Automation

  • Design is completed when an idea is

transformed into architecture or data path description

  • Transforming a design from one form to

another

  • Verifying a design stage output
  • Generating test data
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The Art Of Modeling

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Hardware Description Languages

  • HDLs are used to describe hardware for

the purpose of:

– Modeling – Simulation – Testing – Design – Synthesis – Documentation

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Hardware Description Languages

  • Special purpose HDLs:

– ISPS1, behavioral description HDL – AHPL2, data flow description HDL

  • General purpose HDLs:

– Verilog – VHDL – SystemC

1- Instruction Set Processor Specification 2- A Hardware Programming Language

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Hardware Simulation

Simulation Engine

Simulation Results Test Data Component Library

Automatic test generation

Simulation Hardware Model

HDL Model

  • Simulation time
  • Output details
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Simulator Types

  • Based on HDL:

– Behavioral Simulator – Data Flow Simulator – Gate Level Simulator – Device Simulator

  • Based on Engine:

– Oblivious – Event Driven

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Hardware Synthesis

  • A design aid that automatically transforms

a design description from one form to another is a synthesis tool

  • Many commercial synthesis tools use the
  • utput of the data path design
  • Many commercial synthesis tools have

targeted the FPGA market

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Hardware Synthesis

  • Synthesis process:
  • 1. Resource sharing
  • 2. Logic optimization
  • 3. Binding

a<=b+c; c<=a AND e b c e

Adder

a

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Chapter 2 VHDL Backgroound

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VHDL Features

  • General features

– Describing from system to gate – Concurrency

  • Support for design hierarchy

– Operation of system can be specified based

  • n:
  • Its functionality
  • Its smaller subcomponents
  • Library support
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VHDL Features

  • Sequential statements

– Design based on functionality

  • Generic design

– Some conditions may influence model

  • peration, but it is not necessary to generate

a new model

  • Physical characteristics (delay)
  • Environment parameters (temperature)
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VHDL Features

  • Type declaration (strongly typed language)

– Integer type – Floating point type – Enumerate types – User defined types – Operator overloading – Array types – Composite-type (records)

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VHDL Features

  • Use of subprograms (Function, Procedure)

– Explicit type conversion – Logic unit definition – Operator redefinition – New operation definition

  • Structural specification

– Constructs for specifying structural decomposition of hardware at all levels

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VHDL Features

  • Timing Control

– Schedule values to signals – Delay the actual assignments until a later time – Allow any number of explicitly defined clock – Constructs for edge detection – Setup and hold time specification – Pulse width checking – Setting various time constraints

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Chapter 3 Design Methodology Based on VHDL

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VHDL Elements

  • Components

– Entity – Architecture

  • Packages

– Package declaration – Package body

  • Configuration (binding)

Libraries

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Component Description

Component ARCHITECTUREs Logic Function Component ENTITY Interface to the Real World

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Component Description

ENTITY ComponentName IS input and output ports physical and other parameters END ComponentName; ARCHITECTURE identifier OF ComponentName IS declarations BEGIN specification of model in term of its inputs and influenced by physical and other parameters END identifier;

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Multiple Architecture Specification

ENTITY cpu IS PORT(…) ARCHITECTURE behavioral OF cpu IS ARCHITECTURE rtl OF cpu IS ARCHITECTURE structural OF cpu IS ARCHITECTURE other OF cpu IS

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Packages

PACKAGE PackageName IS Component Declaration. sub-program declarations. type definitions END PackageName; PACKAGE BODY PackageName IS sub-programs. END PackageName;

  • Groups components and utilities used for description
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Configurations

CONFIGURATION ConfName OF ComponentName IS bindings of Entities and Architectures. specifying parameters of a design. END CONFIGURATION;

  • Binds subcomponents of a design to elements of

various libraries

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Libraries

LIBRARY LibName; USE LibName.SubPackage.Scope LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; LIBRARY WORK; USE WORK.util_package.int2bit;

  • Groups packages and components to use in another

design (reusability)

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Top-Down Design

  • Is divide-and-conquer method
  • Is referred to as recursive partitioning until all

sub-components become manageable

Partition(System) IF HardwareMappingOf(System) IS done THEN SaveHardwareOf(System) ELSE FOR EVERY Functionally-Distinct Part_I OF System Partition(Part_I) END FOR; END IF; END Partition;

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Top-Down Design

SUD SSC1 SSC2 SSC3 SSC4 SSC31 SSC32 SSC41 SSC42

SUD: System Under Design SSC: System Sub-Component Design Flow Implementation

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Verification

  • design must be simulated to verify the

designer’s understanding of the problem

  • This simulation must be done for every

SSD

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Top-Down Design with VHDL

  • Design a 8 bit serial adder with

– Two data inputs “a” and “b” – One input control signal “start” – One “Clock” input signal – 8 bit “Result” output – “Ready” output

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Serial Adder – Functionality

Clk 11000111 00001111 11010110 A B Result Ready

1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1

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Serial Adder – Behavioral Model

If ( clk=‘1’ and clk’EVENT) then if(start=‘1’) then count:=0; carry:=0; else IF count<8 then count:=count+1; sum:= a XOR b XOR carry; Carry:=(a AND b) OR (a AND carry) AND (b AND carry); Result<=sum & result(7 downto 1); END IF; end if; if count=8 then ready<=‘1’; else ready<=‘0’; end if; end if;

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Serial Adder – Top Down Design

8 bit Serial Adder FullAdder ShiftRegister 8 bit Counter Flip Flop

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Serial Adder – Data Flow Model

ADDER a b Shift Register

En Si

Counter Flip Flop CarryIn CarryOut Result Clk

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Design Flow

8 bit Serial Adder FullAdder ShiftRegister 8 bit Counter Flip Flop

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Flip Flop Description

ENTITY flop IS GENERIC(td_reset,td_in: TIME:=8 NS); PORT(reset,din,clk: IN BIT; qout: BUFFER:=‘0’); END flop; ARCHITECTURE behavioral OF flop IS BEGIN PROCESS(clk) BEGIN IF(clk=‘0’ AND clk’EVENT) THEN IF reset=‘1’ THEN qout<=‘0’ AFTER td_reset; ELSE qout<=din AFTER td_in; END IF; END IF; END PROCESS; END behavioral;

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Design Flow

8 bit Serial Adder FullAdder ShiftRegister 8 bit Counter Flip Flop

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Full-Adder Description

Entity fulladder IS PORT(a,b,cin: IN BIT;sum,count:OUT BIT); END fulladder; ARCHITECTURE behavioral OF fulladder IS BEGIN Sum<=a XOR b XOR cin; Cout<=(a AND b) OR (a AND cin) OR (b AND cin); END behavioral;

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Design Flow

8 bit Serial Adder FullAdder ShiftRegister 8 bit Counter Flip Flop

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Shifter Description

ENTITY shifter IS PORT(sin,reset,enable,clk:IN BIT; parout BUFFER BIT_VECTOR(7 DOWNTO 0) ); END shifter; ARCHITECTURE dataflow OF shifter IS BEGIN

Sh: BLOCK(clk=‘0’ AND NOT clk’STABLE) BEGIN parout<= GUARDED “00000000” WHEN reset=‘1’ ELSE sin & parout(7 DOWNTO 1) WHEN enable=‘1’ ELSE UNAFFECTED; END BLOCK;

END dataflow;

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Structural Description of Serial Adder

ENTITY serial_adder IS PORT(a,b,start,clock: IN BIT;ready:OUT BIT; Result :BUFFER BIT_VECTOR(7 DOWNTO 0) ); END; ARCHITECTURE structural OF serial_adder IS SIGNAL serial_sum,carry_in,carry_out,counting:BIT; BEGIN

u1:ENTITY WORK.fulladder PORT MAP(a,b,carry_in,serial_sum,carry_out); u2:ENTITY WORK.flop PORT MAP(start,carry_out,clock,carry_in); u3:ENTITY WORK.counter PORT MAP(start,clock,counting); u4:ENTITY WORK.shifter PORT MAP(serial_sum,start,countig,clock,result); u5:ready <= NOT counting;

END;